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參數資料
| 型號： | LMH6550MAX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | Differential, High Speed Op Amp |
| 中文描述： | OP-AMP, 4000 uV OFFSET-MAX, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 13/17頁 |
| 文件大?。?/td> | 854K |
| 代理商： | LMH6550MAX |
Application Section
(Continued)
SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT
The LMH6550 provides excellent performance as an active
balun transformer.
Figure 3
shows a typical application
where an LMH6550 is used to produce a differential signal
from a single ended source. It should be noted that com-
pared to differential input, using a single ended input will
reduce gain by 1/2. So that the closed loop gain will be; Gain
= Av = 0.5 * R
F
/R
G
.
In single ended input operation the output common mode
voltage is set by the V
pin as in fully differential mode.
Also, In this mode the common mode feedback circuit must
recreate the signal that is not present on the unused differ-
ential input pin. The performance chart titled “Balance Error”
is the measurement of the effectiveness of this process. The
common mode feedback circuit is responsible for ensuring
balanced output with a single ended input. Balance error is
defined as the amount of input signal that couples into the
output common mode. It is measured as a the undesired
output common mode swing divided by the signal on the
input. Balance error can be caused by either a channel to
channel gain error, or phase error. Either condition will pro-
duce a common mode shift. The chart titled “Balance Error”
measures the balance error with a single ended input as that
is the most demanding mode of operation for the amplifier.
Supply and V
CM
pin bypassing are also critical in this mode of
operation. See the above section on FULLY DIFFERENTIAL
OPERATION for bypassing recommendations also see
Fig-
ure 4
and
Figure 5
for recommended supply bypassing
configurations.
SINGLE SUPPLY OPERATION
The input stage of the LMH6550 has a built in offset of 0.7V
towards the lower supply to accommodate single supply
operation with single ended inputs.As shown in
Figure 6
, the
input common mode voltage is less than the output common
voltage. It is set by current flowing through the feedback
network from the device output. The input common mode
range of 0.4V to 3.2V places constraints on gain settings.
Possible solutions to this limitation include AC coupling the
input signal, using split power supplies and limiting stage
gain. AC coupling with single supply is shown in
Figure 7
.
In
Figure 6
below closed loop gain =A
= R
/R
G
. Please note
that in single ended to differential operation V
is measured
single ended while V
is measured differentially. This
means that gain is really 1/2 or 6 dB less when measured on
either of the output pins separately.
V
ICM
= Input common mode voltage = (V
+IN
+V
IN
)/2.
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog to digital converters (ADC) present challenging load
conditions. They typically have high impedance inputs with
large and often variable capacitive components. As well,
there are usually current spikes associated with switched
capacitor or sample and hold circuits.
Figure 8
shows a
typical circuit for driving an ADC. The two 56
resistors
serve to isolate the capacitive loading of the ADC from the
amplifier and ensure stability. In addition, the resistors form
part of a low pass filter which helps to provide anti alias and
noise reduction functions. The two 39 pF capacitors help to
smooth the current spikes associated with the internal
switching circuits of the ADC and also are a key component
in the low pass filtering of the ADC input. In the circuit of
Figure 8
the cutoff frequency of the filter is 1/ (2*
π
*56
*(39
pF + 14pF)) = 53MHz (which is slightly less than the sam-
pling frequency). Note that the ADC input capacitance must
be factored into the frequency response of the input filter,
and that being a differential input the effective input capaci-
tance is double. Also as shown in
Figure 8
the input capaci-
tance to many ADCs is variable based on the clock cycle.
See the data sheet for your particular ADC for details.
20130111
FIGURE 6. Relating A
V
to Input/Output Common Mode
Voltages
20130109
FIGURE 7. AC Coupled for Single Supply Operation
L
www.national.com
13
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| LMH6559MF | High-Speed, Closed-Loop Buffer |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LMH6550MAX/NOPB | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMH6550MM | 制造商:Texas Instruments 功能描述:OP Amp Single Volt Fdbk ±6V/12V 8-Pin MSOP T/R 制造商:Texas Instruments 功能描述:OP AMP, DIFF SINGL, SOIC8, POWERWISE 制造商:Texas Instruments 功能描述:Differential High Speed Op Amp,LMH6550MM |
| LMH6550MM/NOPB | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMH6550MMX | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMH6550MMX/NOPB | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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