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參數資料
| 型號： | LMX2355TM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數： | 17/23頁 |
| 文件大小： | 403K |
| 代理商： | LMX2355TM |
Programming Description
(Continued)
5.2 RF_N Register
If the control bits (CTL[2:0]) are 1 1, data is transferred from the 24-bit shift register into the RF_N register latch which sets the
RF PLL’s programmable N counter register and various control functions. The RF N counter consists of a 2-bit A counter, 2-bit B
counter, 11-bit C counter, and a 4-bit fractional counter. For proper operation, C_WORD
^
MAX{A_WORD, B_WORD}+2. Serial
data format is shown below.
MSB
RF_CTL_WORD
[2:0]
23
LSB
C_WORD [10:0]
B_WORD [1:0]
A_WORD [1:0]
FRAC_CONT [3:0]
1
1
21 20
10 9
8
7
6 5
2 1
0
5.2.1.1 RF_CTL_WORD
(RF_N[21]–RF_N[23])
MSB
LSB
RF_CNT_RST
PWDN_RF
PRESC_SEL
5.2.1.2 RF/IF Control Word Truth Table
BIT
FUNCTION
0
1
IF_CNT_RST/RF_CNT_RST
PWDN_IF/PWDN_RF
PWDN_MODE
IF/RF counter reset
IF/RF power down
Power down mode
select
Prescaler Modulus
Select
Normal Operation
Powered up
Asynchronous power
down
8/9/12/13
0.5 GHz–1.2 GHz
Reset
Powered down
Synchronous power
down
16/17/20/21
1.2 GHZ–2.5 GHZ
PRESC_SEL
LMX2354
The
Counter Reset
enable bit when activated allows the reset of both N and R counters. Upon powering up, the N counter
resumes counting in “close” alignment with the R counter (the maximum error is one prescaler cycle).
Activation of the PLL
power down
bits result in the disabling of the respective N counter divider and de-biasing of its respective
fin inputs (to a high impedance state). The respective R counter functionality also becomes disabled when the power down bit is
activated. The OSC
pin reverts to a high impedance state when both RF and IF power down bits are asserted. Power down
forces the respective charge pump and phase comparator logic to a TRI-STATE condition. The MICROWIRE control register
remains active and capable of loading and latching in data during all of the power down modes.
Both synchronous and asynchronous power down modes are available with the LMX235x family in order to adapt to different
types of applications. The power down mode bit IF_N[21] is used to select between synchronous and asynchronous power down.
The MICROWIRE control register remains active and capable of loading and latching in data during all of the power down modes.
Synchronous Power Down Mode
One of the PLL loops can be synchronouslypowered down by first setting the power down mode bit HIGH (IF_N[21] = 1) and then
asserting its power down bit (IF_N[22] or RF_N[22] = 1). The power down function is gated by the charge pump. Once the power
down bit is loaded, the part will go into power down mode upon the completion of a charge pump pulse event.
Asynchronous Power Down Mode
One of the PLL loops can be asynchronously powered down by first setting the power down mode bit LOW (IF_N[21] = 0) and
then asserting its power down bit (IF_N[22] or RF_N[22] = 1). The power down function is NOT gated by the charge pump. Once
the power down bit is loaded, the part will go into power down mode immediately.
Prescaler select
is used to set the RF prescaler. The LMX2354 contains quadruple modulus prescalers. It uses the 16/17/20/21
prescaler mode to operate at 1.2 GHz–2.5 GHz. In addition, it can use the 8/9/12/13 prescaler to operate at 550 MHz–1.2 GHz.
L
www.national.com
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