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參數資料
| 型號： | LMX2355TM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數： | 3/23頁 |
| 文件大小： | 403K |
| 代理商： | LMX2355TM |
Pin Descriptions
Pin No. for
TSSOP
Package
1
2
Pin No. for
CSP
Package
24
1
Pin
Name
I/O
Description
OUT0
V
CC
RF
O
—
Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
RF PLL power supply voltage input. Must be equal to Vcc
IF
. May range from
2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
Power supply for RF charge pump. Must be
≥
V
CC
RF
and V
CC
IF
.
RF charge pump output. Connected to a loop filter for driving the control input
of an external VCO.
Ground for RF PLL digital circuitry.
RF prescaler input. Small signal input from the VCO.
RF prescaler complimentary input. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
Ground for RF PLL analog circuitry.
Dual mode oscillator output or RF R counter input. Has a V
CC
/2 input threshold
when configured as an input and can be driven from an external CMOS or TTL
logic gate.
Oscillator input which can be configured to drive both the IF and RF R counter
inputs or only the IF R counter depending on the state of the OSC
programming bit. (See functional description 1.1 and programming description
3.1.)
Multiplexed output of N or R divider and RF/IF lock detect. CMOS output. (See
programming description 3.1.5.)
RF PLL Enable. Powers down RF N and R counters, prescaler, and
TRI-STATE
charge pump output when LOW. Bringing RF_EN high powers up
RF PLL depending on the state of RF_CTL_WORD. (See functional description
1.9.)
IF PLL Enable. Powers down IF N and R counters, prescaler, and TRI-STATE
charge pump output when LOW. Bringing IF_EN high powers up IF PLL
depending on the state of IF_CTL_WORD. (See functional description 1.9.)
High impedance CMOS Clock input. Data for the various counters is clocked
into the 24-bit shift register on the rising edge.
Binary serial data input. Data entered MSB first. The last two bits are the
control bits. High impedance CMOS input.
Load Enable high impedance CMOS input. Data stored in the shift registers is
loaded into one of the 4 internal latches when LE goes HIGH. (See functional
description 1.7.)
Ground for IF analog circuitry.
IF prescaler complimentary input. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
IF prescaler input. Small signal input from the VCO.
Ground for IF digital circuitry.
IF charge pump output. For connection to a loop filter for driving the input of an
external VCO.
Power supply for IF charge pump. Must be
≥
V
CC
RF
and V
CC
IF
.
IF power supply voltage input. Must be equal to V
CC
RF
. Input may range from
2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
Programmable CMOS output. Level of the output is controlled by IF_N [18] bit.
3
4
2
3
V
P
RF
CP
o
RF
—
O
5
6
7
4
5
6
GND
fin RF
fin RF
—
I
I
8
9
7
8
GND
OSC
RF
—
I
10
9
OSC
IF
I
11
10
Fo/LD
O
12
11
RF_EN
I
13
12
IF_EN
I
14
13
CLOCK
I
15
14
DATA
I
16
15
LE
I
17
18
16
17
GND
fin IF
—
I
19
20
21
18
19
20
fin IF
GND
CPo
IF
I
—
O
22
23
21
22
V
PIF
V
CC
IF
—
—
24
23
OUT1
O
L
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