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參數(shù)資料
| 型號： | LMX2433SLEX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Dual High Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3600 MHz, PQCC20 |
| 封裝： | PLASTIC, UTCSP-20 |
| 文件頁數(shù)： | 32/49頁 |
| 文件大小： | 943K |
| 代理商： | LMX2433SLEX |
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LMX243x FinRF Input Impedance Test Setup
20053591
The block diagram above illustrates the setup required to
measure the LMX243x device’s RF input impedance. The
same setup is used for the LMX2430TM Evaluation Board.
Measuring the device’s input impedance facilitates the de-
sign of appropriate matching networks to match the PLL to
the VCO, or in more critical situations, to the characteristic
impedance of the printed circuit board (PCB) trace, to pre-
vent undesired transmission line effects. The FinIF input
impedance is evaluated in the same way.
Before the actual measurements are taken, the Network
Analyzer needs to be calibrated, i.e. the error coefficients
need to be calculated. The Network Analyzer’s calibration
standard is used to calculate these coefficients. The calibra-
tion standard includes an open, short and a matched load. A
1-port calibration is implemented here.
To calculate the coefficients, the PLL chip is first removed
from the PCB. A piece of semi-rigid coaxial cable is then
soldered to the pad on the PCB which is equivalent to the
FinRF pin on the PLL chip. Proper grounding near the ex-
posed tip of the semi-rigid coaxial cable is required for
accurate results. Note that the DC blocking capacitor is
removed for this test. The Network Analyzer port is then
connected to the other end of the semi-rigid coaxial cable. In
this way, the semi-rigid coaxial cable acts as a transmission
line. This transmission line adds electrical length and pro-
duces an offset from the reference plane of the Network
Analyzer; therefore, it must be included in the calibration.
The desired operating frequency is then set. The typical
frequency range selected for the LMX243x device’s RF syn-
thesizer is from 100 MHz to 6000 MHz.
The Network Analyzer calculates the calibration coefficients
based on the measured S
11
parameters. With this all done,
calibration is now complete.
The PLL chip is then placed on the PCB. A power supply is
then connected to Vcc. The EN, ENosc, and OSCin pins are
all tied to Vcc. Alternatively, the OSCin pin can be tied to
ground. In this setup, the complementary input (FinRF
*
) is
AC coupled to ground. With the Network Analyzer still con-
nected to the semi-rigid coaxial cable, the measured FinRF
impedance is displayed.
The OSCin input impedance is measured in the same way.
The impedance is measured when the oscillator buffer is
powered up (ENosc is set HIGH) and when the oscillator
buffer is powered down (ENosc pin is set LOW).
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2433SLEX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2433TM | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Dual 250MHz to 3600MHz 20-Pin TSSOP Rail |
| LMX2433TM/NOPB | 功能描述:鎖相環(huán) - PLL 3.6Ghz High Freq Dual Pll RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2433TMX | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2433TMX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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