- 您現在的位置：買賣IC網 > PDF目錄361044 > LMX2531LQ1700E (NATIONAL SEMICONDUCTOR CORP) PLLatinum High Performance Frequency Synthesizer System with Integrated VCO PDF資料下載
參數資料
| 型號： | LMX2531LQ1700E |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum High Performance Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36 |
| 文件頁數： | 20/25頁 |
| 文件大小： | 589K |
| 代理商： | LMX2531LQ1700E |
2.0 General Programming Information
(Continued)
2.6 REGISTER R5
2.6.1 EN_PLL -- Enable Bit for PLL
When this bit is set to 1, the PLL is powered up, otherwise, it is powered down.
2.6.2 EN_VCO -- Enable Bit for the VCO
When this bit is set to 1, the VCO is powered up, otherwise, it is powered down.
2.6.3 EN_OSC -- Enable Bit for the Oscillator Inverter
When this bit is set to 1 (default), the reference oscillator is powered up, otherwise it is powered down.
2.6.4 EN_VCOLDO -- Enable Bit for the VCO LDO
When this bit is set to 1 (default), the VCO LDO is powered up, otherwise it is powered down.
2.6.5 EN_PLLLDO1 -- Enable Bit for the PLLLDO 1
When this bit is set to 1 (default), the PLLLDO 1 is powered up, otherwise it is powered down.
2.6.6 EN_PLLLDO2 -- Enable Bit for the PLLLDO 2
When this bit is set to 1 (default), the PLLLDO 2 is powered up, otherwise it is powered down.
2.6.6 EN_PLLLDO2 -- Enable Bit for the PLLLDO 2
When this bit is set to 1 (default), the PLLLDO 2 is powered up, otherwise it is powered down.
2.6.7 EN_DIGLDO -- Enable Bit for the Digital LDO
When this bit is set to 1 (default), the Digital LDO is powered up, otherwise it is powered down.
2.6.8 REG_RST -- Resets all registers to default settings
This bit needs to be programmed three times to initialize the part. When this bit is set to one, all registers are set to default mode,
and the part is powered down. The second time the R5 register is programmed with REG_RST=0, the register reset is released
and the default states are still in the registers. However, since the default states for the blocks and LDOs is powered off, it is
therefore necessary to program R5 a third time so that all the LDOs and blocks can be programmed to a power up state.When
this bit is set to 1, all registers are set to the default modes, but part is powered down. For normal operation, this bit is set to 0.
Note that once this initialization is done, it is not necessary to initialize the part any more.
L
www.national.com
20
相關PDF資料 |
PDF描述 |
|---|---|
| LMX4268 | Radio Transceiver for DECT |
| LMX5080MX | PLLatinum⑩ 2.7 GHz Low Power Dual Modulus Prescaler for RF Personal Communications |
| LMX5080M | PLLatinum⑩ 2.7 GHz Low Power Dual Modulus Prescaler for RF Personal Communications |
| LMX5080 | PLLatinum⑩ 2.7 GHz Low Power Dual Modulus Prescaler for RF Personal Communications |
| LMX9820ASMX | Bluetooth Serial Port Module |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LMX2531LQ1700E/NOPB | 功能描述:鎖相環 - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2531LQ1742 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:SYNTHESIZER SYSTEM POWERWISE SMD |
| LMX2531LQ1742/NOPB | 功能描述:鎖相環 - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2531LQ1742FPEB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Evaluation Board Operating Instructions |
| LMX2531LQ1778E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum High Performance Frequency Synthesizer System with Integrated VCO |
發布緊急采購，3分鐘左右您將得到回復。