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參數(shù)資料
| 型號(hào)： | LMX2531LQ1910E |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum High Performance Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36 |
| 文件頁(yè)數(shù)： | 20/25頁(yè) |
| 文件大小： | 589K |
| 代理商： | LMX2531LQ1910E |
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2.0 General Programming Information
(Continued)
2.6 REGISTER R5
2.6.1 EN_PLL -- Enable Bit for PLL
When this bit is set to 1, the PLL is powered up, otherwise, it is powered down.
2.6.2 EN_VCO -- Enable Bit for the VCO
When this bit is set to 1, the VCO is powered up, otherwise, it is powered down.
2.6.3 EN_OSC -- Enable Bit for the Oscillator Inverter
When this bit is set to 1 (default), the reference oscillator is powered up, otherwise it is powered down.
2.6.4 EN_VCOLDO -- Enable Bit for the VCO LDO
When this bit is set to 1 (default), the VCO LDO is powered up, otherwise it is powered down.
2.6.5 EN_PLLLDO1 -- Enable Bit for the PLLLDO 1
When this bit is set to 1 (default), the PLLLDO 1 is powered up, otherwise it is powered down.
2.6.6 EN_PLLLDO2 -- Enable Bit for the PLLLDO 2
When this bit is set to 1 (default), the PLLLDO 2 is powered up, otherwise it is powered down.
2.6.6 EN_PLLLDO2 -- Enable Bit for the PLLLDO 2
When this bit is set to 1 (default), the PLLLDO 2 is powered up, otherwise it is powered down.
2.6.7 EN_DIGLDO -- Enable Bit for the Digital LDO
When this bit is set to 1 (default), the Digital LDO is powered up, otherwise it is powered down.
2.6.8 REG_RST -- Resets all registers to default settings
This bit needs to be programmed three times to initialize the part. When this bit is set to one, all registers are set to default mode,
and the part is powered down. The second time the R5 register is programmed with REG_RST=0, the register reset is released
and the default states are still in the registers. However, since the default states for the blocks and LDOs is powered off, it is
therefore necessary to program R5 a third time so that all the LDOs and blocks can be programmed to a power up state.When
this bit is set to 1, all registers are set to the default modes, but part is powered down. For normal operation, this bit is set to 0.
Note that once this initialization is done, it is not necessary to initialize the part any more.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LMX2531LQ1910E/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2531LQ1950/NOPB | 功能描述:IC PLL FREQ SYNTH W/VCO 36-LLP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PowerWise® 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2531LQ2010E/NOPB | 功能描述:IC PLL FREQ SYNTH W/VCO 36-LLP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PowerWise® 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2531LQ2080E | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 1904MHz to 2274MHz 36-Pin LLP EP T/R |
| LMX2531LQ2080E/NOPB | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 HIGH PERF FREQUENCY SYNTHESIZER SYSTEM RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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