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參數資料
| 型號： | LTC1421ISW-2.5#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 12/24頁 |
| 文件大小： | 329K |
| 描述： | IC CONTROLLER HOT SWAP 24-SOIC |
| 標準包裝： | 32 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 3 V ~ 12 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC |
| 包裝： | 管件 |
12
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
U
U
U
When V
CCLO
collapses, there is enough energy stored on
the 1礔 capacitor connected to AUXV
CC
to keep the gate
discharge circuitry alive long enough to fully turn off the
external N-channels.
Power N-Channel Selection
The R
DS(ON)
of the external pass transistor must be low
enough so that the voltage drop across it is about 200mV
or less at full current. If the R
DS(ON)
is too high, the voltage
drop across the transistor might cause the output voltage
to trip the reset circuit. Table 2 lists the transistors that are
recommended for use with the LTC1421.
Table 2. N-Channel Selection Guide
CURRENT
PART
LEVEL (A)
NUMBER
MANUFACTURER DESCRIPTION
0 to 1
MMDF2N02E ON Semiconductor Dual N-Channel SO-8
R
DS(ON)
= 0.1&
1 to 2
MMDF3NO2HD ON Semiconductor Dual N-Channel SO-8
R
DS(ON)
= 0.09&
2 to 5
MTB30N06
ON Semiconductor Single 30A
N-Channel DD Pak
R
DS(ON)
= 0.05&
5 to 10
MTB50N06E ON Semiconductor Single
N-Channel DD Pak
R
DS(ON)
= 0.025&
10 to 20
MTB75N05HD ON Semiconductor Single
N-Channel DD Pak
R
DS(ON)
= 0.0095&
Data Bus
When a board is inserted or removed from the host, care
must be given to prevent the system data bus from being
corrupted when the data pins make or break contact. One
problem is that the fully discharged input or output capaci-
tance of the logic gates on the board will draw an inrush
current when the data bus pins first make contact. The
inrush current can temporarily corrupt the data bus, but
usually will not cause long term damage. The problem can
be minimized by insuring the input or output data bus
capacitance is kept as small as possible.
The second, and more serious problem involves the
diodes to V
CC
at the input and output of most logic families
(Figure 12).
V
CC
OUT
BACKPLANE
BOARD
D1
D2
1421 F12
DATA
BUS
Figure 12. Typical Logic Gate Loading the Data Bus
Figure 13: Buffering the Data Bus
+
21 20
C
LOAD
22
23
5
12
24
3
14
4
17
7
18
8
21
11
22
12
2
15
5
16
6
SYSTEM
DATA BUS
BOARD
DATA BUS
19
9
20
10
23
1
13
QS3384 V
CC
GND
1421 F13
V
CC
5V
LTC1421
R1
0.005&
Q1
MTB50N06E
GND
DISABLE
4
3
2
1
With the board initially unpowered, the V
CC
input to the
logic gate is at ground potential. When the data bus pins
make contact, the bus line is clamped to ground through
the input diode D1 to V
CC
. Large amounts of current can
flow through the diode and cause the logic gate to latch up
and destroy itself when the power is finally applied. This
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