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參數資料
型號: LTC1642CGN#TRPBF
廠商: Linear Technology
文件頁數: 9/16頁
文件大小: 243K
描述: IC CONTROLLER HOTSWAP ADJ 16SSOP
標準包裝: 2,500
類型: 熱交換控制器
應用: 通用型 Infiniband?
內部開關:
電源電壓: 2.97 V ~ 16.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-SSOP
包裝: 帶卷 (TR)
9
LTC1642
1642fb
APPLICATIO  S I FOR  ATIO
U
U
U
Hot Circuit Insertion
When a circuit board is inserted into a live backplane its
supply bypass capacitors can draw large currents from the
backplane power bus as they charge. These currents can
permanently damage connector pins and can glitch the
backplane supply, resetting other boards in the system.
The LTC1642 limits the charging currents drawn by a
boards capacitors, allowing safe insertion into a live
backplane.
In the circuit shown in Figure 1 the LTC1642 and the
external NMOS pass transistor Q1 work together to limit
charging currents. Waveforms at board insertion are
shown in Figure 2. When power is first applied to V
CC
 the
chip holds Q1s gate at ground. After an adjustable delay
a 25礎 current source begins to charge the external
capacitor C2, so choose C2 to limit the inrush current
I
INRUSH
 charging the boards bypass capacitance C
LOAD
according to the equation:
 
C2   C
"
25  A
I
LOAD
INRUSH
=
?/DIV>
An internal charge pump supplies the 25礎 gate current,
ensuring sufficient gate drive to Q1. At 3V V
CC
 the minimum
gate drive is 4.5V; at 5V V
CC
 the minimum is 10V; at 15V V
CC
the minimum is again 4.5V, due to an internal zener clamp
from the GATE pin to ground. Resistor R3 limits this zeners
transient current during board insertion and removal and
protects against high frequency oscillations in Q1. D1
provides additional protection against supply spikes.
The delay before the GATE pin voltage begins ramping is
determined by the system timer. It comprises an external
capacitor C1 from the RST TMR pin to ground; an internal
2礎 current source feeding RST TMR from V
CC
; an internal
comparator, with the noninverting input tied to RST TMR
and the inverting input tied to the 1.22V reference; and an
internal NMOS pull-down. In standby, the NMOS holds
RST TMR at ground. When the timer starts the NMOS
turns off and the RST TMR voltage ramps up as the current
source charges the capacitor. When RST TMR reaches
1.22V the timer comparator trips, the GATE voltage begins
ramping up and RST TMR returns to ground. The timer
delay is:
t
RSTTMR
 = (615ms/礔) C1.
The second RST TMR cycle indicates that V
OUT
 is within
tolerance; it is discussed in the Undervoltage Monitor
section.
GATE
ON
14
SENSE
15
FAULT
6
4
BRK TMR
2
V
CC
16
R2
0.010&
Q1
FDS6630A
GND
LTC1642
8
RST TMR
3
1642 F01
R3
100&
R4
330&
D1
1N4705
18V
C2
0.047礔
C
LOAD
+
C1
0.33礔
C4
0.33礔
ALL RESISTORS ?% UNLESS NOTED
RESET DELAY = 200ms
SHORT-CIRCUIT DURATION = 10ms
V
IN
12V
2.5A
V
OUT
R7
24k
R10
30k
Figure 1. Supply Control Circuitry
Powering-Up in Current Limit
Ramping the GATE pin voltage limits the current to I =
25礎 " C
LOAD
/C2, where C2 is the external capacitor
connected to the GATE and C
LOAD
 is the load capacitance.
If the value of C
LOAD
 is uncertain, then a worst-case design
can often result in needlessly long ramp times, and it may
be better to limit the charging current by powering up in
current limit.
Current Limiting and Solid-State Circuit Breaker
The current can be limited by connecting a sense resistor
between the LTC1642s V
CC
 and SENSE pins. When the
voltage drop across this resistor reaches a limiting value,
Figure 2. Timing at Board Insertion
100ms/DIV
1642 F02
OV
10V/DIV
RST TMR
2V/DIV
GATE
20V/DIV
V
OUT
20V/DIV
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