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參數資料
型號: LTC3445EUF#TRPBF
廠商: Linear Technology
文件頁數: 21/24頁
文件大小: 475K
描述: IC REG TRPL BUCK/LINEAR 24-QFN
標準包裝: 2,500
拓撲: 降壓(降壓)(1),線性(LDO)(2)
功能: 任何功能
輸出數: 3
頻率 - 開關: 1.5MHz
電壓/電流 - 輸出 1: 0.85 V ~ 1.55 V,600mA
電壓/電流 - 輸出 2: 可調至0.6V,50mA
電壓/電流 - 輸出 3: 可調至0.6V,50mA
帶 LED 驅動器:
帶監控器:
帶序列發生器:
電源電壓: 2.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應商設備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 帶卷 (TR)
21
LTC3445
3445fa
As an example, consider the LTC3445 in dropout at an
input voltage of 2.7V, an ambient temperature of 70癈, a
buck load current of 600mA, LDO1 set to 1.3V with a load
of 25mA, LDO2 set to 1.1V with a load of 15mA, and the
PowerPath regulator at 2.5V with a load of 6礎. From the
typical performance graph of switch resistance, the R
DS(ON)
of the P-channel switch at 70癈 is approximately 0.52&.
Therefore, power dissipated by the part is:
P
D(BUCK)
 = I
LOAD
 
2
 " R
DS(ON)
 = 180mW
P
D(LDO1)
 = (2.7  1.3)V " 0.025A = 35mW
P
D(LDO2)
 = (2.7  1.1)V " 0.015A = 24mW
P
D(PowerPath)
 = (2.7  2.5)V " 6礎 = 1.2礧
P
D(TOTAL)
 = 0.239W
For the QFN24 package, the ?/DIV>
JA
 is 37癈/W. Thus, the
junction temperature of the regulator is:
T
J
 = 70癈 + (0.239)(37) = 78.8癈
which is well below the maximum junction temperature of
125癈. Note that at higher supply voltages, the junction
temperature is lower due to reduced switch resistance
(R
DS(ON)
).
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3445. These items are also illustrated graphically in
Figures 9 and 10. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace, the V
CC1
 trace and the V
CC2
 trace should be kept
short, direct and wide.
2. Does the FB pin connect directly to the output voltage
reference? Ensure that there is no load current running
from the reference voltage and the FB pin.
3. Does the (+) plate of C
IN1
 connect to V
CC1
 as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
FB node.
5. Keep the () plates of C
IN
 and C
OUT
 as close as possible.
APPLICATIO S I FOR ATIO
U
U
U
Figure 9
Figure 10
V
CC1
10
V
CC1
GND
OUT
3445 F09
SW
RUN
FB
GND
25
NC
12
GND
11
NC
13
SW
14
RUN
15
NC
16
VIA TO
OUT
VIA TO
FB
FB
17
C
IN
C
OUT
L1
V
CC1
10
3445 f10
GND
25
L1
V
OUT
BOLD LINES INDICATE HIGH CURRENT PATH
V
CC1
C
IN
NC
12
GND
11
NC
13
SW
14
RUN
15
NC
16
FB
17
C
OUT
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