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參數資料
| 型號： | LTC3670EDDB#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 10/12頁 |
| 文件大小： | 210K |
| 描述： | IC REG TRPL BCK/LINEAR 12DFN |
| 標準包裝： | 2,500 |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（2） |
| 功能： | 任何功能 |
| 輸出數： | 3 |
| 頻率 - 開關： | 2.25MHz |
| 電壓/電流 - 輸出 1： | 可調至0.8V，400mA |
| 電壓/電流 - 輸出 2： | 可調至0.8V，150mA |
| 電壓/電流 - 輸出 3： | 可調至0.8V，150mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 無 |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 12-DFN-EP（3x2） |
| 包裝： | 帶卷 (TR) |
LTC3670
10
3670f
APPLICATIONS INFORMATION
Input/Output Capacitor Selection
Low ESR (equivalent series resistance) ceramic capacitors
should be used to bypass the following pins to ground:
V
IN
, the buck output, LDO1 and LDO2. Only X5R or X7R
ceramic capacitors should be used because they retain
their capacitance over wider voltage and temperature
ranges than other ceramic types. A 10糉 output capaci-
tor is suf cient for the buck regulator output. For good
transient response and stability the output capacitor for
the buck regulator should retain at least 4糉 of capacitance
over operating temperature and bias voltage. The V
IN
pin
should be bypassed with a 2.2糉 capacitor. The LDO1
and LDO2 output pins should each be bypassed with a
1糉 capacitor or greater. Larger values yield improved
transient response.
Consult with capacitor manufacturers for detailed infor-
mation and speci cations on their selection of ceramic
capacitors. Many manufacturers now offer very thin (<1mm
tall) ceramic capacitors ideal for use in height-restricted
designs. Table 2 shows a list of several ceramic capacitor
manufacturers.
Table 2. Ceramic Capacitor Manufacturers
AVX
www.avxcorp.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Vishay Siliconix
www.vishay.com
TDK
www.tdk.com
Output Voltage Programming
Figure 1 shows how feedback resistor dividers are con-
nected to the LTC3670 to set the output voltages of the
buck and an LDO.
The output voltage of the buck regulator is determined by
R1 and R2, following the equation:
V
R
R
V
OUTBUCK
( )
" .
= +
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
1
2
1
08
An LDOs output voltage is similarly determined by R3
and R4, following:
V
R
R
V
OUTLDO
( )
" .
= +
?/DIV>
?/DIV>
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?/DIV>
?/DIV>
?/DIV>
?/DIV>
1
4
3
08
Typical values for R2 and R4 are in the range from 40k
to 1M.
For improved buck regulator transient response, the capaci-
tor C
FB
cancels the pole created by the feedback resistors
and the input capacitance of the BUCKFB pin. A variety of
capacitor sizes can be used for C
FB
, but a value of 10pF
is recommended for most applications. Experimentation
with capacitor sizes between 2pF and 22pF may yield
improved transient response.
Printed Circuit Board Layout Considerations
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3670:
1) The Exposed Pad of the package should connect directly
to a large ground plane to minimize thermal and electri-
cal impedance.
2) The connection from the input supply pin (V
IN
) to its
decoupling capacitor should be kept as short as pos-
sible. The GND side of this capacitor should connect
directly to the ground plane of the part. The V
IN
capacitor
provides the AC current to the buck regulators power
MOSFETs and their drivers. It is especially important
to minimize PCB trace inductance from this capacitor
to the V
IN
and GND pins of the LTC3670.
3) The switching power trace connecting the SW pin to the
inductor should be kept as short as possible to reduce
radiated EMI and parasitic coupling.
4) The LDO output capacitors should be placed as close to
the IC as possible, and connected to the LDO outputs
and the GND pin as directly as possible.
LTC3670
SW
R2
R1
V
OUT(BUCK)
V
OUT(LDO)
3670 F01
C
FB
BUCKFB
LDO
LDO_FB
R4
R3
Figure 1. Setting the Output Voltages of the LTC3670
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