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參數資料
| 型號： | LTC4223CDHD-2#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 15/24頁 |
| 文件大小： | 290K |
| 描述： | IC CNTRLR HOT SWAP DUAL 16-DFN |
| 標準包裝： | 73 |
| 類型： | 熱交換控制器 |
| 應用： | ATCA，MicroTCA? |
| 內部開關： | 無 |
| 電源電壓： | 2.7 V ~ 6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 16-DFN（5x4） |
| 包裝： | 管件 |
LTC4223-1/LTC4223-2
15
422312f
APPLICATIONS INFORMATION
Power-Good Monitor
Internal circuitry monitors the output voltages, AUXOUT
and 12V
OUT
. The power-good status is reported via their
respective open drain outputs,
?/DIV>
A
?/DIV>
U
?/DIV>
X
?/DIV>
P
?/DIV>
G
?/DIV>
O
?/DIV>
O
?/DIV>
D and
?/DIV>
1
?/DIV>
2
?/DIV>
P
?/DIV>
G
?/DIV>
O
?/DIV>
O
?/DIV>
D.
Several conditions must be met before the power-good
outputs assert low.
1. The monitored output should be above its power-
good threshold and hysteresis.
2. The input supply is above undervoltage lockout.
3.
?/DIV>
E
?/DIV>
N is low.
4. The associated ON pin is high.
5. Thermal shutdown is not activated.
If any of the supply outputs falls below its power-good
threshold for more than 20約, the respective power-good
output will be pulled high by the external pull-up resistor
or internal 10糀 pull-up.
Resetting Faults (LTC4223-1)
Any supply faults tripping the circuit breaker are latched
and
?/DIV>
F
?/DIV>
A
?/DIV>
U
?/DIV>
L
?/DIV>
T asserts low. For the latched-off version
(LTC4223-1), to reset a fault latch due to overcurrent or
thermal shutdown on auxiliary supply, pull both AUXON and
12ON pins low together for at least 100約, after which the
?/DIV>
F
?/DIV>
A
?/DIV>
U
?/DIV>
L
?/DIV>
T will go high. Toggling both the ON pins high together
again initiates the debounce timing cycle, thereafter the
auxiliary supply starts up rst followed by 12V supply. To
skip the debounce timing cycle, rst pull only AUXON low
then high for at least 50約 before toggling 12ON low then
high. The fault latch clears on the falling edge of 12ON
and the auxiliary supply powers up. Thereafter, the 12V
supply powers up if 12ON pulls high.
To reset a fault on the 12V supply and re-start the output,
toggle only the 12ON pin low and then high again. Tog-
gling the
?/DIV>
E
?/DIV>
N pin high then low again or bringing the bias
input, V
CC
below its UVLO threshold for more than 100約
will initiate the debounce timing cycle and reset all fault
latches before power-up. Bringing AUXIN or 12V
IN
below its
undervoltage threshold will not reset the fault latches. For
the auto-retry version (LTC4223-2), the latched fault will
be cleared automatically after a cool-off timing cycle.
Auto-Retry after a Fault (LTC4223-2)
At time point 1 in Figure 8, if a fault latched-off the 3.3V
auxiliary supply after power-up, a cool-off cycle begins.
The TIMER capacitor charges up to 1.235V with a 10糀
current and then discharges with a 2糀 current to 0.2V at
time point 3. This is followed by a debounce timing cycle
whereby the fault latch is cleared, and
?/DIV>
F
?/DIV>
A
?/DIV>
U
?/DIV>
L
?/DIV>
T pulls high
when TIMER reaches its threshold at time point 4. At the
end of debounce cycle, the internal switch is allowed to
turn on. If the output short persists, the auxiliary supply
powers up into a short with active current limiting. At time
point 7, the fault lter delay begins with TIMER ramping
up with a 10糀 current. If the TIMER times out at time
point 8,
?/DIV>
F
?/DIV>
A
?/DIV>
U
?/DIV>
L
?/DIV>
T will be pulled low and a new cool-off cycle
begins with TIMER ramping down with a 2糀 current.
The whole process repeats itself until the output-short
is removed.
In Figure 9, a fault latches off the 12V supply at time point
1; a cool-off cycle begins by discharging the TIMER ca-
pacitor with 2糀 current from 1.235V to 0.2V threshold.
At time point 2 a new debounce timing cycle is initiated
where the fault latch is cleared, and
?/DIV>
F
?/DIV>
A
?/DIV>
U
?/DIV>
L
?/DIV>
T pulls high when
TIMER reaches its threshold at time point 3. At the end of
the debounce cycle, the 12V GATE is allowed to start up. If
the output short persists, the 12V supply powers up into a
short with active current limiting. At time point 6, the fault
lter delay begins with TIMER ramping up with a 200糀
current. The TIMER times out at time point 7,
?/DIV>
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F
?/DIV>
A
?/DIV>
U
?/DIV>
L
?/DIV>
T pulls
low and a new cool-off cycle begins with TIMER ramping
down with a 2糀 current. The whole process repeats itself
until the output-short is removed.
The auto-retry duty cycle is given by:
DutyCycle
t
t
t
t
FILTER
COOL DEBOUNCE FILT
=
+
+
"
%
100
EER
For example, if TIMER capacitor, C
T
= 0.1糉, the auto-retry
duty cycle for auxiliary and 12V supply is 6.5% and 0.5%
respectively.
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| LTC4223CDHD-2TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual Supply Hot Swap Controller for Advanced Mezzanine Card |
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