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參數資料
| 型號： | LU3X32FT |
| 廠商： | Lineage Power |
| 英文描述： | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網收發器) |
| 中文描述： | 雙端口3伏10/100以太網收發器德克薩斯州/外匯（3伏雙端口1000萬位和100米位以太網收發器） |
| 文件頁數： | 1/54頁 |
| 文件大小： | 626K |
| 代理商： | LU3X32FT |
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Preliminary Data Sheet
July 2000
LU3X32FT Two-Port 3 V 10/100 Ethernet Transceiver TX/FX
Note:For sustaining support only, not for new
designs.
Overview
The LU3X32FT is a fully integrated two-port 10
Mbits/s/100 Mbits/s physical layer device with
transceiver. This part was designed for 10 Mbits/s/
100 Mbits/s applications where board space, cost,
and power are at a premium and stringent functional
interoperability is a necessity. Operating at 3.3 V, the
LU3X32FT is a powerful device for the forward
migration of legacy 10 Mbits/s products and
noncompliant 100 Mbits/s devices. The LU3X32FT
was designed from the beginning to conform fully
with all pertinent specifications, from the ISO/IEC
11801 and EIA/TIA 568 cabling guidelines to ANSI
X3.263 TP-PMD to IEEE* 802.3 ethernet
specifications.
Features
I
Single-chip integrated two-port physical layer and
transceiver for 10Base-T and/or 100Base-T func-
tions
I
IEEE 802.3 compatible 10Base-T and 100Base-T
physical layer interface and ANSI X3.263 TP-PMD
compatible transceiver
I
PECL interface for external FX transceiver
I
Built-in analog 10 Mbits/s receive filter, removing
the need for external filters
I
Built-in 10 Mbits/s transmit filter
I
10 Mbits/s PLL exceeding tolerances for both pre-
amble and data jitter
I
100 Mbits/s PLL, combined with the digital adap-
tive equalizer, robustly handles variations in rise-
fall time, excessive attenuation due to channel
loss, duty-cycle distortion, crosstalk, and baseline
wander
I
Transmit rise-fall time manipulated to provide lower
emissions, amplitude fully compatible for proper
interoperability
I
Programmable scrambler seed for better FCC
compliancy
I
Selectable CIM, Class II support, and powerful MII
drivers for repeater applications
I
IEEE 802.3U clause 28 compliant autonegotiation
for full 10 Mbits/s and 100 Mbits/s control
I
Fully configurable via pins and management
accesses
I
PHY MIB support
I
Symbol mode option
I
Low-power –300 mA max
I
Low autonegotiation power –30 mA/port
I
Very low powerdown mode <5 mA/port
I
128-pin TQFP package
* IEEEis a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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