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參數資料
| 型號： | LUC4AS01 |
| 廠商： | Lineage Power |
| 英文描述： | ATM Switch Element (ASX)(ATM開關元件) |
| 中文描述： | ATM交換機元素（澳大利亞）（自動柜員機開關元件） |
| 文件頁數： | 1/6頁 |
| 文件大小： | 177K |
| 代理商： | LUC4AS01 |
Advance Product Brief
March 1997
LUC4AS01
ATM Switch Element (ASX)
S
LUCENT TECHNOLOGIES—PROPRIETARY
Use pursuant to Company Instructions
Introduction
The ASX IC is part of the ATLANTA chip set consist-
ing of four devices that provide a highly integrated,
innovative, and complete VLSI solution for imple-
menting the ATM layer core of an ATM switch system.
The chip set enables construction of high-perfor-
mance, feature-rich, and cost-effective ATM switches,
scalable over a wide range of switching capacities.
This document discusses the ASX device.
Features
I
Functions as a highly efficient, 5 Gbits/s, shared
memory, ATM switching element for scalable
switch fabrics up to 25 Gbits/s.
— In stand-alone mode, used as an 8 x 8 switch
fabric with 622 Mbits/s I/O rates.
— Can be used as a building block for larger N x N
fabrics of up to 40 x 40 ports with 622 Mbits/s
I/O rate (25 Gbits/s total ATM throughput).
— In three-stage mode, supports variable expan-
sion factors (4:8, 5:8, and 6:8) for more compact
fabric design with higher port density.
Works with other ATLANTA devices to provide total
system solutions for ATM switching.
— Directly interfaces with the LUC4AB01 ATM
Buffer Manager (ABM) chip to support port card
buffering.
— Directly interfaces with the LUC4AC01 ATM
Crossbar Element (ACE) chip for constructing
larger nonblocking, lossless, and self-routing
switch fabrics, organized into a three-stage
topology.
Incorporates a novel internal backpressure algo-
rithm based on separate on-chip queues for all fab-
ric ports to enable large scale cell buffers on the
port cards (up to 32K cells per port) using cost-
effective commonly available SRAMs.
Has an internal 512 cell memory, fully shared
across all queues, supplemented by the port card
buffers.
Supports four delay priorities per queue and uses
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a programmable, weighted, round-robin scheduler
for servicing delay priorities.
Provides efficient unrestricted multicasting with
single copy storage.
Incorporates independent clocking of input ports to
facilitate robust distributed systems designs by
allowing for independent port card clocks or arbi-
trary clock skew introduced across backplanes
from separate port cards.
Uses differential clocking to provide noise immu-
nity. Parity and cell insertion/extraction aid in
detecting and tracking system errors.
Provides system diagnostic features, including
detection and reporting of the following error condi-
tions:
— Input port parity error.
— Input port overrun error.
— Loss of input port clock.
— CRC error on outgoing cell.
— Linked list fault indication.
— Test cell extraction.
Provides several performance/traffic indicators.
Supports a generic
Intel
* or
16-bit microprocessor interface with interrupt.
Facilitates circuit board testing with on-chip
standard boundary-scan.
Fabricated as a low-power monolithic IC in 0.5
3.3 V CMOS technology, with 5 V tolerant and TTL-
level compatible I/O.
Available in a 388-pin PBGA package.
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Motorola
compatible
I
IEEE
I
μ
m,
I
*
Intel
Motorola
IEEE
Electronics Engineers, Inc.
is a registered trademark of Intel Corporation.
is a registered trademark of Motorola, Inc.
is a registered trademark of The Institute of Electrical and
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LUC4AS01-BC7-DB | 制造商:Agere Systems 功能描述: |
| LUC4AU01SC5DB | 制造商:LUCENT 功能描述:* |
| LUC4AU01-SC5-DB | 制造商:Agere Systems 功能描述: |
| LUC4AU01-SC6 | 制造商:Alcatel-Lucent 功能描述: 制造商:LUCENT 功能描述: |
| LUC4AU01-SC6-DB | 制造商:Alcatel-Lucent 功能描述:Electronic Component |
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