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參數資料
| 型號： | M5M4V16G50DFP-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
| 中文描述： | 1,600（2 -銀行甲262144字× 32位）同步圖形RAM |
| 文件頁數： | 1/33頁 |
| 文件大?。?/td> | 167K |
| 代理商： | M5M4V16G50DFP-8 |
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M5M4V16G50DFP -8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0)
DESCRIPTION
The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM,
with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M5M4V16G50DFP can operate at frequencies of 100+ MHz. The
BLOCK WRITE and WRITE-PER-BIT functions provide improved performance
in graphic memory systems.
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequencies of 125 MHz
- Fully synchronous operation referenced to clock rising edge
- Dual bank operation controlled by A10(Bank Address)
- Internal pipelined operation: column address can be changed every clock cycle
- Programmable /CAS Latency (
LVTTL:
2 and 3)
- Programmable Burst Length (1/2/4/8 and Full Page)
- Programmable Burst Type (Sequential / Interleave)
- Byte control using DQM0 - DQM3 signals in both read and write cycles
- Persistent Write-Per-Bit (WPB) function
- 8 Column Block Write (BW) function
- Auto Precharge / All bank precharge controlled by A9
- Auto Refresh and Self Refresh Capability
- 2048 refresh cycles /32ms
- LVTTL Interface
- 100 pin QFP package with 0.65mm lead pitch
Max.
Frequency
CLK Access
Time
M5M4V16G50DFP - 8
125MHz
7ns
M5M4V16G50DFP- 10
100MHz
8ns
PRELIMINARY
Some of contents are described for general products
and are subject to change without notice.
M5M4V16G50DFP- 12
83MHz
10ns
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