- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380324 > MACH4-96 (Lattice Semiconductor Corporation) High-Performance EE CMOS Programmable Logic PDF資料下載
參數(shù)資料
| 型號： | MACH4-96 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | 高性能電子工程CMOS可編程邏輯 |
| 文件頁數(shù)： | 1/33頁 |
| 文件大小： | 294K |
| 代理商： | MACH4-96 |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
FINAL
Publication#
21535
Amendment/
+1
Rev:
A
Issue Date:
November 1997
1
M
MACH 4 FAMILY
1
COM’L: -15
IND: -18
MACH4-96/96-15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
N
144 Pins in PQFP
96 Macrocells
15 ns t
PD
47.6 MHz f
102 Inputs with pull-up resistors
96 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs
96 Flip-flops
Up to 20 product terms per macrocell, with XOR
Flexible clocking
— Four global clock pins with selectable edges
— Asynchronous mode available for each macrocell
3 MACH111SP-size blocks
SpeedLocking
for guaranteed fixed timing
JTAG, 5-V, in-system programmable
JTAG (IEEE 1149.1) boundary scan testing capability
Input and output switch matrices for high routability
N
N
Commercial, 18 ns t
PD
Industrial
N
CNT
N
N
N
N
N
N
N
N
N
N
PLEASE NOTE
This device is currently dual-marked with the MACH355 ordering part number. The dual-mark
scheme will facilitate design and manufacturing flows until we have completely phased in the new
M4-96/96 nomenclature. Please use the MACH355 data sheet (PID# 17467) as a reference.
: The MACH4-96/96 (M4-96/96) reflects a new nomenclature for the MACH
4 Family.
GENERAL DESCRIPTION
The MACH4-96/96 (M4-96/96) is a member of Vantis’ high-performance EE CMOS MACH 4 family.
This device has approximately three times the macrocell capability of the popular MACH111SP,
with significant additional density and functional features.
The M4-96/96 consists of six PAL
The central switch matrix connects the PAL blocks to each other and to all input pins, providing a
high degree of connectivity between the PAL blocks. This allows designs to be placed and routed
efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix.
The input switch matrix provides input signals with alternative paths into the central switch matrix;
the output switch matrix provides flexibility in assigning macrocells to I/O pins.
blocks interconnected by a programmable central switch matrix.
Lattice Semiconductor
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH4 | High Performance E 2 CMOS In-System Programmable Logic |
| MACH435Q-20JC | High-Density EE CMOS Programmable Logic |
| MACH435Q-25JC | High-Density EE CMOS Programmable Logic |
| MACH435-12 | High-Density EE CMOS Programmable Logic |
| MACH435-12JC | High-Density EE CMOS Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH4-96/96-15YC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH4-SK44 | 制造商:Lattice Semiconductor Corporation 功能描述:MACH STARTER KIT |
| MACH5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| MACH5-256/68-7YC-10YI | 制造商:Advanced Micro Devices 功能描述: |
| MACHLV210-12 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Density EE CMOS Programmable Logic |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。