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參數資料
| 型號： | MAX5934EEE+ |
| 廠商： | Maxim Integrated |
| 文件頁數： | 3/15頁 |
| 文件大小： | 268K |
| 描述： | IC HOT-SWAP CONTROLLER 16-QSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 100 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 33 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 管件 |
Positive High-Voltage, Hot-Swap Controllers with
Selectable Fault Management and Status Polarity
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +24V (MAX5934A), V
CC
= +48V (MAX5934), GND = 0V, T
A
= -40癈 to +85癈, unless otherwise noted. Typical values are at
T
A
= +25癈.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC = 3.75%, DC = floating
1.5
3
4.5
DC = 1.88%, DC = high
0.75
1.5
2.25
TIMER Pulldown Current
I
TIMERON
V
TIMER
= 1V
DC = 0.94%, DC = low
0.37
0.75
1.12
礎
ON High Threshold
V
ONH
ON low-to-high transition
1.280
1.313
1.355
V
ON Low Threshold
V
ONL
ON high-to-low transition
1.221
1.233
1.245
V
ON Hysteresis
V
ONHYST
80
mV
ON Input Bias Current
I
INON
V
ON
= 0V
-1
+1
礎
LATCH/RETRY and POL_SEL
Low-Voltage Threshold
V
LRIL
,
V
POS_SEL_IL
0.4
V
LATCH/RETRY and POL_SEL
High-Voltage Threshold
V
LRIH
,
V
POS_SEL_IH
3.2
V
V
POL_SEL
= 80V
4.5
LATCH/RETRY and POL_SEL
Input Current
I
LR_IN
,
I
POS_SEL_IN
V
POL_SEL
= 0V
-37
礎
Source GATE Clamp Voltage
V
SGZ
V
GATE
- V
OUT
15
16.4
19
V
I
O
= 2mA
0.4
PWRGD_ Output Low Voltage
V
OL
I
O
= 4mA
2.5
V
PWRGD_ Leakage Current
I
OH
V
PWRGD_
= 80V
10
礎
Thermal Shutdown
Temperature rising
+150
癈
Thermal-Shutdown Hysteresis
20
癈
SENSE Input Bias Current
I
SENSE
V
SENSE
= 0 to V
CC
-1
+3
礎
DC High-Voltage Threshold 1
V
DCHTH
Ri si ng ed g e, D
C tr ansi ti on fr om 3.75% to
1.88%
2.150
2.600
2.850
V
DC High-Voltage Threshold 2
V
DCLTH
Ri si ng ed g e, D
C tr ansi ti on fr om 0.94% to
3.75%
1.075
1.250
1.425
V
DC High-Voltage Threshold 1
Hysteresis
V
DCLHYS
45
mV
DC High-Voltage Threshold 2
Hysteresis
V
DCLHYS
45
mV
DC Input Open-Circuit Voltage
V
DCOC
1.9
V
DC Input Impedance
R
DC_IN
57
k&
V
_DC
= 80V
50
DC Input Current
I
DC_IN
V
_DC
= 0V
-34
礎
ON Low-to-GATE Low
Propagation Delay
t
PHLON
C
GATE
= 0, Figures 1 and 2
6
祍
ON High-to-GATE High
Propagation Delay
t
PLHON
C
GATE
= 0, Figures 1 and 2
1.7
祍
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