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參數資料
| 型號： | MAX5965AEAX+ |
| 廠商： | Maxim Integrated |
| 文件頁數： | 25/54頁 |
| 文件大?。?/td> | 1334K |
| 描述： | IC PSE CTRLR FOR POE 36SSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 30 |
| 類型： | 以太網供電控制器（PoE） |
| 應用： | IP 電話，LAN 網絡供電，網絡路由器和交換機 |
| 內部開關： | 無 |
| 電源電壓： | 2.4 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 36-SSOP |
| 包裝： | 管件 |
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High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
______________________________________________________________________________________ 25
Serial Addressing
Each transmission consists of a START condition (Figure
6) sent by a master, followed by the MAX5965A/
MAX5965B 7-bit slave address plus R/W bit, a register
address byte, one or more data bytes, and finally a
STOP condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master fin-
ishes communicating with the slave, the master issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The STOP condition frees the
bus for another transmission.
Bit Transfer
Each clock pulse transfers one data bit (Figure 7). The
data on SDA must remain stable while SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 8) that
the recipient uses to handshake receipt of each byte of
data. Thus each byte effectively transferred requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA (or the SDAOUT in the 3-wire
interface) during the acknowledge clock pulse, so that
the SDA line is stable low during the high period of the
clock pulse. When the master transmits to the
MAX5965A/MAX5965B, the MAX5965A/MAX5965B
generate the acknowledge bit. When the MAX5965A/
MAX5965B transmit to the master, the master gener-
ates the acknowledge bit.
Figure 6. START and STOP Conditions
START
STOP
S
P
SDA/
SDAIN
SCL
Figure 7. Bit Transfer
SDA
SCL
DATA LINE STABLE;
DATA VALID
.
CHANGE OF
DATA ALLOWED
Figure 8. Acknowledge
SCL
SDA
BY TRANSMITTER
CLOCK PULSE FOR ACKNOWLEDGEMENT
START CONDITION
SDA
BY RECEIVER
1
2
8
9
S
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MAX5965AEAX+ | 功能描述:熱插拔功率分布 Quad PSE Controller for POE RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5965AEAX+T | 功能描述:熱插拔功率分布 Quad PSE Controller for POE RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5965AUAX+ | 功能描述:熱插拔功率分布 Quad PSE Controller for POE RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5965AUAX+T | 功能描述:熱插拔功率分布 Quad PSE Controller for POE RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5965BCAX+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
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