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參數資料
| 型號： | MAX5969DETE+T |
| 廠商： | Maxim Integrated |
| 文件頁數： | 4/16頁 |
| 文件大小： | 1236K |
| 描述： | IC CTRLR INTERFCE W/MOSFT 16TQFN |
| 標準包裝： | 2,500 |
| 類型： | 以太網供電控制器 PD 開關（PoE） |
| 應用： | 遠程外設（工業控制，相機，數據訪問） |
| 內部開關： | 是 |
| 電流限制： | 720mA 至 880mA |
| 電源電壓： | 60V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WQFN 裸露焊盤 |
| 供應商設備封裝： | 16-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
4 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= (V
DD
- V
SS
) = 48V, R
DET
= 24.9k? R
CLS
= 615? and R
SL
= 60.4k? RTN, WAD, PG, and 2EC unconnected, all voltages are
referenced to V
SS,
unless otherwise noted. T
A
= T
J
= -40NC to +85NC, unless otherwise noted. Typical values are at T
A
= +25NC.)
(Note 3)
Note 3: This device is 100% production tested at T
A
= +25NC. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 1.
Note 5: Effective differential input resistance is defined as the differential resistance between V
DD
and V
SS
. See Figure 1.
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
Note 8: A 20V glitch on input voltage, which takes V
DD
below V
ON
shorter than or equal to t
OFF_DLY
does not cause the
MAX5969D to exit power-on mode.
Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload
condition across V
DD
and RTN.
Figure 1. Effective Differential Input Resistance/Offset Current
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PG Sink Current
V
RTN
= 1.5V, V
PG
= 0.8V, during inrush
period
125
230
375
FA
PG Off-Leakage Current
V
PG
= 60V
1
FA
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
T
SD
T
J
rising
+140
NC
Thermal-Shutdown Hysteresis
T
J
falling
28
NC
I
IN
I
INi + 1
I
INi
I
OFFSET
dR
i
1V
V
INi
V
INi + 1
I
OFFSET
= I
INi
-
V
INi
dR
i
dR
i
=
(V
INi + 1
- V
INi
)
=
1V
(I
INi + 1
- I
INi
)
(I
INi + 1
- I
INi
)
V
IN
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