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參數資料
型號: MAX5981BETE+
廠商: Maxim Integrated
文件頁數: 8/16頁
文件大小: 1328K
描述: IC CTRLR PD IEEE 802.3AF 16TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
類型: 以太網供電控制器 PD 開關(PoE)
應用: 供電設備(PSE)
內部開關:
電流限制: 720mA 至 880mA
電源電壓: 31 V ~ 60 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WQFN 裸露焊盤
供應商設備封裝: 16-TQFN-EP(5x5)
包裝: 管件
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET
8 ______________________________________________________________________________________
  Pin Description (continued)
PIN
NAME
FUNCTION
11
2EC
2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is enabled at 2EC
when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE, the 2EC current
sink is enabled after the isolation MOSFET is fully on until V
IN
 drops below the UVLO threshold. 2EC is
latched when powered by a Type 2 PSE until V
IN
 drops below the reset threshold. 2EC also asserts
when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. 2EC is not
latched if asserted by WAD. The 2EC current sink is turned off when the device is in sleep mode.
12
CLS
Classification Resistor Input. Connect a resistor (R
CLS
) from CLS to V
SS
 to set the desired classification
current. See the classification current specifications in the Electrical Characteristics table to find the resistor
value for a particular PD classification.
13
LED
LED Driver Output. During sleep mode, LED sources a periodic current (I
LED
). The amplitude of I
LED
 is
set by R
SL
according to the formula I
LED
 (in A) = 645.75/(R
SL
 + 1200).
14
SL
Sleep Mode Enable Input. A falling edge on SL brings the device into sleep mode (V
SL
 must drop below
0.75V). An external resistor (R
SL
) connected between SL and V
SS
 sets the LED current (I
LED
).
15
WK
Wake Mode Enable Input. WK has an internal 2.5kI pullup resistor to the internal 5V bias rail. A falling
edge on WK brings the device out of sleep mode and into the normal operating mode (wake mode).
16
ULP
Ultra-Low-Power Enable Input (in Sleep Mode). ULP has an internal 50kI pullup resistor to the internal
5V bias rail. A falling edge on SL while ULP is asserted low enables ultra-low-power mode. When ultra-
low-power mode is enabled, the power consumption of the device is reduced even lower than normal
sleep while still supporting MPS.

EP
Exposed Pad. Do not use EP as an electrical connection to V
SS
. EP is internally connected to V
SS
 
through a resistive path and must be connected to V
SS
 externally. To optimize power dissipation, solder
the exposed pad to a large copper power plane.
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