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參數資料
| 型號： | MB40D001PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | DAC |
| 英文描述： | D/A Converter for Digital Tuning |
| 中文描述： | SERIAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24 |
| 封裝： | PLASTIC, SSOP-24 |
| 文件頁數： | 14/17頁 |
| 文件大小： | 214K |
| 代理商： | MB40D001PFV |
14
MB40D001
I
DATA INPUT/OUTPUT TIMING
(Serial Bus Format)
Timing of D/A Converter Operation, I/O Expander Operation (serial to parallel conversion), and ESR Write
Operation.
Data input is enabled at the fall of the CS signal. 16-bit data is input, and executed by shift register command
at the rise of CS.
In D/A converter operation, analog output selected at the rise of CS is converted. In serial to parallel conversion,
digital output selected at the rise of CS is converted. In ESR write operation, data is set in the ESR at the rise of
[CS] and used to change pin states.
I/O Expander Operation (parallel to serial conversion)
Data input is enabled at the fall of the CS signal. 16-bit data (parallel to serial conversion command) is input,
and commands received at the rise of CS. At the fall of CS the data from parallel input is loaded in the shift register
from D4 to DF, and output from the SO pin timed to the fall of the CLK signal.
D0
D1
D2
DE
DF
1
2
3
15
16
SI
CLK
CS
SO
AO
×
D
××
1
1
2
16
16
D0
DF
D0
DF
SI
CLK
CS
SO
D
××
(Parallel to serial conversion command entered)
(Parallel to serial conversion result output)
Parallel data loaded
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