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參數資料
| 型號： | MB40D001PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | DAC |
| 英文描述： | D/A Converter for Digital Tuning |
| 中文描述： | SERIAL, PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24 |
| 封裝： | PLASTIC, SSOP-24 |
| 文件頁數： | 7/17頁 |
| 文件大小： | 214K |
| 代理商： | MB40D001PFV |
7
MB40D001
I/O Expander [Channel select = “1101”]: Serial
→
Parallel Conversion
Performs parallel conversion of data bits D4 to DF for output on pins D
0
to D
11
.
Note that only those pins designated for output in the ESR (expander status register) are output.
I/O Expander [Channel select = “1110”]: Parallel
→
Serial Conversion
Writes data from D
0
to D
11
pins to bits D4 to DF in the shift register.
Data is output to the SO pin on the shift clock (CLK) signal (The first 4 bits output data D0 to D3, so the
converted output should be read as data bits 5 through 16.).
Note that the data value is “0” for pins designated for output in the ESR (expander status register) as well as
analog output pins.
Expander Status Register [Channel select = “1111”]
Setting
Pin status
“0”
Input standby status (Hi-Z output)
D
11
to D
4
pins used for analog output should be set to “0”.
Output state
“1”
DF
↓
D
11
D
10
DE DD DC DB DA
↓
↓
↓
D
9
D
8
D9
↓
D
5
D8
↓
D
4
D7
↓
D
3
D6
↓
D
2
D5
↓
D
1
D4
↓
D
0
D3
D2
D1
D0
↓
D
7
↓
D
6
Shift register
Parallel I/O pins (output state)
DF
↑
D
11
D
10
DE DD DC DB DA
↑
↑
↑
D
9
D
8
D9
↑
D
5
D8
↑
D
4
D7
↑
D
3
D6
↑
D
2
D5
↑
D
1
D4
↑
D
0
D3
D2
D1
D0
↑
D
7
↑
D
6
Shift register
Parallel I/O pins (output state)
DF
↓
D
11
D
10
DE DD DC DB DA
↓
↓
↓
D
9
D
8
D9
↓
D
5
D8
↓
D
4
D7
↓
D
3
D6
↓
D
2
D5
↓
D
1
D4
↓
D
0
↓
D
7
↓
D
6
Shift register
This register sets the status of each pin.
ESR
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