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參數(shù)資料
| 型號(hào)： | MB81ES653225-12L |
| 廠商： | Fujitsu Limited |
| 英文描述： | Consumer/Embedded Application Specific Memory for SiP |
| 中文描述： | 消費(fèi)/嵌入式SIP應(yīng)用程序特定的內(nèi)存 |
| 文件頁數(shù)： | 18/44頁 |
| 文件大小： | 485K |
| 代理商： | MB81ES653225-12L |
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MB81ES653225-12/-12L
18
18. MODE REGISTER SET (MRS)
The mode register of SDR I/F FCRAM provides a variety of different operations. The register consists of five
operation fields; Burst Length, Burst Type, CAS latency, Operation Code and Page length. Refer to “
■
MODE
REGISTER TABLE”. The mode register can be programmed by the Mode Register Set command (MRS) . Once
a mode register is programmed, the contents of the register will be held until re-programmed by another MRS
command. MRS command should only be issued on condition that all DQ is in Hi-Z. The condition of the mode
register is undefined after the power-up stage. It is required to set each field after initialization of SDR I/F FCRAM.
Refer to “22. POWER-UP INITIALIZATION”.
19. EXTENDED MODE REGISTER SET (EMRS)
The extended mode register consists of two operation fields; Partial Array Self Refresh (PASR) and Temperature
Compensated Self Refresh (TCSR) . Refer to “
■
MODE REGISTER TABLE”. The condition of the extended
mode register is undefined after the Power-up stage. It is required to set each field after initialization of SDR I/F
FCRAM. Refer to “22. POWER-UP INITIALIZATION”.
20. PARTIAL ARRAY SELF REFRESH (PASR)
Memory array size to be refreshed during self refresh operation is programmable in order to reduce self refresh
current. Data outside the defined area will not be retained during self refresh.
21. TEMPERATURE COMPENSATED SELF REFRESH (TCSR)
Programmable refresh rate for self refresh mode allows the system to control power as a function of temperature.
22. POWER-UP INITIALIZATION
The SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following
Power On Sequence to execute read or write operation.
1. Apply power (V
DD
should be applied before or in parallel with V
DDQ
) and start clock. Attempt to maintain either
NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100
μ
s.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL) .
4. Assert minimum of 2 Auto-refresh command (REF) .
5. Program the mode register by Mode Register Set command (MRS) .
6. Program the extended mode register by Extended Mode Register Set command (EMRS) .
In addition, it is recommended DQM and CKE track V
DD
to insure that output is High-Z state. The Mode Register
Set command (MRS) and Extended Mode Register Set command (EMRS) can be set before 2 Auto-refresh
command (REF) .
23. DISABLE MODE
When DSE is applied high level, SDR I/F FCRAM entries Disable mode. Disable mode entry doesn’t require
clock. In Disable mode, SDR I/F FCRAM current consumption is less than I
DD2PS
and the output is High-Z. Any
command isn’t accepted in this mode. To exit Disable mode, apply Low level to DSE.
24. SELF BURNIN MODE
When BME is applied High level, SDR I/F FCRAM entries Self Burnin mode. Self Burnin mode entry doesn’t
require clock. In SELF BURNIN mode, self refresh command is asserted internally. Any command isn’t accepted
in this mode. To exit Self Burnin mode, apply Low level to BME.
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