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參數資料
| 型號： | MB84VP24491HK |
| 廠商： | Fujitsu Limited |
| 英文描述： | 128M (X16) FLASH MEMORY 32M (X16) Mobile FCRAMTM |
| 中文描述： | 128M的（x16）的快閃記憶體32M的（x16）的移動FCRAMTM |
| 文件頁數： | 28/70頁 |
| 文件大小： | 1272K |
| 代理商： | MB84VP24491HK |
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MB84VP24491HK
-70
27
(Continued)
Legend:
RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A
22
, A
21
, A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and
A
12
will uniquely select any sector.
BA = Bank Address. Address settled by A
22
, A
21
, A
20
, A
19
will select Bank A, Bank B, Bank C and Bank D.
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
SGA = Sector group address to be protected.
WPH = (A
7
, A
6
, A
5
, A
4
, A
3
, A
2
, A
1
, A
0
) is (0, 0, 0, 0, 0, 0, 1, 0)
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
HRA = Address of the HiddenROM area
Word Mode : 000000h to 00007Fh
HRBA = Bank Address of the HiddenROM area (A
22
= A
21
= A
20
= V
IL
)
RD (0) = Read Data bit. If protected, DQ
0
= 1, if unprotected, DQ
0
= 0
RD (1) = Read Data bit. If protected, DQ
1
= 1, if unprotected, DQ
1
= 0
OPBP = (A
7
, A
6
, A
5
, A
4
, A
3
, A
2
, A
1
, A
0
) is (0, 0, 0, 1, 1, 0, 1, 0)
PWA/PWD = Password Address/Password Data
PL = (A
7
, A
6
, A
5
, A
4
, A
3
, A
2
, A
1
, A
0
) is (0, 0, 0, 0, 1, 0, 1, 0)
SPML = (A
7
, A
6
, A
5
, A
4
, A
3
, A
2
, A
1
, A
0
) is (0, 0, 0, 1, 0, 0, 1, 0)
WP = (A
7
, A
6
, A
5
, A
4
, A
3
, A
2
, A
1
, A
0
) is (0, 0, 0, 0, 0, 0, 1, 0)
*1:This command is valid during Fast Mode.
*2:This command is valid while RESET = V
ID
.
*3: This command is valid during HiddenROM mode.
*4:The data “00h” is also acceptable.
Notes :
Address bits A
22
to A
11
= X = “H” or “L” for all address commands except for
PA, SA, BA, SGA, OPBP PWA, PL, SPML, WP WPH.
Bus operations are defined in this document.
The system should generate the following address patterns:
Word Mode : 555h or 2AAh to addresses A
10
to A
0
Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
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