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15.7 Notes on Using the I
2
C
15.7 Notes on Using the I
2
C
This section describes precautions to take when using the I
2
C interface.
I
Precaution in Setting the I
2
C Interface Register
Before writing to the bus control register (IBCR), the I
2
C interface must be enabled (ICCR: EN).
When the master slave selection bit (IBCR: MSS) is set, transfer starts.
I
Precaution in Setting the Shift Clock Frequency
To calculate the shift clock frequency using the F
sck
expression (1) in Table 15.4-3 "Functions of
Each Bit in I
2
C Clock Control Register (ICCR)", it is necessary to know the values of m, n, and
DMBP.
When n is 4 (ICCR: CS2 = CS1 = CS0 = 0), "DMBP = 1" cannot be selected. Other
combinations do not present a problem.
I
Precaution on the Priority at Simultaneous Writing
Contention of the next byte transfer and stop condition
When "0" is written to IBCR: MSS in states where IBCR: INT is cleared, the MSS bit has a
higher priority and a stop condition is generated.
Contention of the next byte transfer and start condition
When "1" is written to IBCR: SCC in states where IBCR: INT is cleared, the SCC bit has a
higher priority and a start condition is generated.
I
Precaution on Setting with Software
Do not select the repeated start condition (IBCR: EN = 0) and the slave mode (IBCR: MSS = 0)
at the same time.
In states where the interrupt request flag bits (BER and INT in the IBCR register) are set to "1"
and the interrupt request enable bits are enabled (BEIE and INTE in the IBCR register are set to
"1"), recovery from the interrupt processing cannot be performed. Clear the BER and INT bits in
the IBCR register.
When the I
2
C operation is not permitted (ICCR: EN = 0), all bits of the bus status register IBSR
and the bus control register IBCR (excluding the bus error BER bit and the bus error enable
BEIE bit) are cleared.