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CHAPTER 16 MULTI-ADDRESS I
2
C
Note:
When the interrupt request flag bit (MBCR: BER) is cleared, do not rewrite the interrupt
request enable bit (MBCR: BEIE) simultaneously.
Only when the multi-address I
2
C enable bit (MCCR: EN) is set, values can be written to the
ACK, GCAA, and INTE bits in the MBCR register.
Bit 1
INTE:
Transfer end interrupt
request enable bit
This bit selects whether an interrupt at the end of transfer is
enabled (INTE = 1) or disabled (INTE = 0).
When this bit is set and INT is set to "1," a transfer end
interrupt request is sent to the CPU.
Bit 0
INT:
Transfer end interrupt
request flag bit
With this bit, the data transfer end interrupt request flag can
be cleared. In addition, it can be determined whether the
interrupt is detected.
When "0" is written, the transfer end interrupt request flag is
cleared. When "1" is written, no change occurs.
If any of the following four conditions is met when one byte
transfer including the acknowledge bit is completed
(including the acknowledge bit in the 9th clock), this bit is set
to "1."
Bus master mode
Addressed slave
A general call address is received
Arbitration lost is generated
When this bit is set to "1," the SCL line is kept at the "L" level.
This bit is cleared when "0" is written to this bit. At this time,
this macro releases the SCL line and transfers the next byte.
This bit is also cleared to "0" when a start or stop condition is
generated in master mode.
Note:
1) If "1" is written to SCC when INT = 0, "1" in the SCC bit
has a higher priority and a start condition is generated.
2) If "0" is written to MSS when INT = 0, "0" in the MSS bit
has a higher priority and the stop condition is
generated.
For RMW instructions, "1" is always read.
Table 16.4-2 Function of Each Bit in Multi-address I
2
C Bus Controller Register (MBCR) (Continued)
Bit name
Function