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CHAPTER 4 I/O PORT
4.5.2
Operation of Port 3
This section describes the operations of port 3.
I
Operation of Port 3
H
Operation as an output port
If data is written into the PDR3 register, data is retained on the output latch. If the value of
the output latch is "0", the output transistor is turned "ON" and the "L" level is output to the
pins. If the value of the output latch is "1", the output transistor is turned "OFF" and the pins
are put into high impedance. When the output pins are pulled up, the port is pulled up if the
value of the output latch is "1".
H
Operation as an input port
Pin values can be read by reading the PDR3 register.
H
Operation during a reset
If CPU is reset, the value of the PDR3 register is initialized to "1". Thus, all output transistors
are turned "OFF" and the pins are put into in high impedance.
H
Operation during resource output
To use resources, set the output enable bit of each resource. Since the resource output
takes precedence, settings of the PDR3 register corresponding to the resource output pins
have no significance.
H
Operation in stop mode and watch mode
If the pin state designate bit (STBC: SPL) of the standby control register is set to "1" when a
transition to the stop mode or watch mode occurs, the output transistor is forced "OFF" and the
pins are put into high impedance. The input is fixed to prevent leakage due to input opening.
Table 4.5-4 "Pin States of Port 3" lists the pin states of port 3.
Table 4.5-4 Pin States of Port 3
Pin name
Normal operation
Main sleep
Main stop (SPL=0)
Sub-sleep
Sub-stop (SPL=0)
Watch mode (SPL=0)
Main stop (SPL=1)
Sub-stop (SPL=1)
Watch mode (SPL=1)
During reset
P30 to P35
General-purpose I/O port/
resource I/O
Hi-Z
Hi-Z
SPL: Pin state designate bit of the standby control register (STBC: SPL)
Hi-Z: High impedance