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| 型號(hào)： | MB91661PMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 1/132頁(yè) |
| 文件大小： | 4189K |
| 代理商： | MB91661PMC |
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FUJITSU MICROELECTRONICS
DATA SHEET
Copyright2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.2
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
32-bit Microcontrollers
CMOS
FR80 MB91660 Series
MB91661/F662/664/V650
■ DESCRIPTION
The MB91660 series is a line of Fujitsu microcontrollers based on a 32-bit RISC CPU core that feature a variety
of peripheral functions for embedded applications that demand high-performance and high-speed CPU process-
ing.
This series is based on the FR80* family CPU and is implemented as a single chip.
* : FR is a line of products of FUJITSU MICROELECTRONICS Limited.
■ FEATURES
FR80 CPU
32-bit RISC, load/store architecture, five-stage pipeline
General-purpose registers : 32-bit
× 16
16-bit fixed-length instructions (basic instructions) : 1 instruction per cycle
Instructions suitable for embedded applications
- Memory-to-memory transfer, bit processing, barrel shift instructions, etc.
- Instruction support for high level languages
Function entry and exit instructions, instructions for register multi-load and multi-store
- Bit search instruction
“1” detection, “0” detection, transition point detection
- Branch instructions with delay slots
Reduced overhead when processing branches
- Register interlock functions
Facilitate coding in assembly language
- Built-in multiplier/instruction-level support
- Signed 32-bit multiplication
: 5 cycles
- Signed 16-bit multiplication
: 3 cycles
- Interrupts (save PC and PS) : 6 cycles, 16 priority levels
- Harvard architecture allowing program access and data access to be executed simultaneously
- The prefetch function for instructions using the 4-word instruction queue in the CPU
(Continued)
DS07-16905-3E
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