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參數資料
型號: MBC13900T1
廠商: MOTOROLA INC
元件分類: 小信號晶體管
英文描述: NPN Silicon Low Noise Transistor
中文描述: L BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR
封裝: ULTRA SMALL, PLASTIC, CASE 318M, SC-70, 4 PIN
文件頁數: 11/26頁
文件大小: 813K
代理商: MBC13900T1
Applications Information
MOTOROLA
MBC13900
Technical Data
For More Information On This Product,
Go to: www.freescale.com
11
Figure 19. 900 MHz LNA Board Layout
3.2 1900 MHz LNA
Figure Figure 20 shows the schematic and Figure 21 shows the component placement for a 1900 MHz
LNA. The design goals for the circuit are:
NF < 1.35 dB
Gain > 14 dB
Return Loss > 10 dB, input and output
Unconditional stability from 100 MHz to 6 GHz.
Typical performance that can be expected from this circuit at 3.0 V V
CC
and 5.0 mA is listed in Table 5.
The component values can be changed to enhance the performance of a particular parameter but usually at
the expense of another. Gain can be improved by sacrificing stability (R3 and R5). Input return loss can be
sacrificed to improve noise figure. Input return loss can be improved at the expense of noise figure (C3,
C7, L4). IIP3 can be improved by increasing emitter degeneration (L3) and bias current (R2). Unused
traces are available on the PCB to add emitter degeneration at leads 1 and 3 of the device.
Table 4. Typical 900 MHz LNA Performance
V
CC
I
C
(mA)
NF
(dB)
50
Insertion
Gain (dB)
Output IP3
(dBm)
Input Return
Loss (dB)
Output
Return
Loss (dB)
3.0
5.0
1.2
19.7
15
10.1
10.2
3.5
6.1
1.21
20.2
17.6
10.8
10.8
Gnd
V
CC
C1
R
C4
R
L
C2
R3
C5
R2
R
L
C
C3
R6
Component Value
C1
C2
C3
C4
C5
C6
L1
L2
L3
R1
R2
R3
R4
R5
R6
Vias
PCB
Comments
Optional Bypassing
DC Block and S
22
DC Block and S
Broadband bypass
Broadband bypass
IIP3 improvement
Toko LL1608-FS, match, bias
Toko LL1608-FH, match, bias
Emitter L on board (distance to GND vias)
Bias
Bias
Stability, S
22
Jumper
Stability, S
22
Jumper
D = 15 mil
ε
r
=4.5, h=25 mil, t=1.75 mil
1.0 μF
3.3 pF
12 pF
0.01 μF
1.0 μF
0.3 pF
6.8 nH
5.6 nH
<0.5 nH
133
49.9 k
16.5
0
3.9
0
FR4
F
Freescale Semiconductor, Inc.
n
.
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