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參數(shù)資料
| 型號： | MC100EP809FAG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 1:9 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 100EP |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 2 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVDS，LVPECL |
| 輸出： | HSTL |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | MC100EP809FAGOS |
Semiconductor Components Industries, LLC, 2008
May, 2008 Rev. 9
1
Publication Order Number:
MC100EP809/D
MC100EP809
3.3V1:9 Differential
HSTL/PECL/LVDS to HSTL
Clock Driver with LVTTL
Clock Select and Enable
Description
The MC100EP809 is a low skew 1to9 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
one differential HSTL and one differential LVPECL. Both input pairs
can accept LVDS levels. They are selected by the CLK_SEL pin
which is LVTTL. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE), which is LVTTL,
is synchronous ensuring the outputs will only be enabled/disabled
when they are already in LOW state (Figure 9).
The MC100EP809 guarantees low outputtooutput skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. The MC100EP809 output structure uses open
emitter architecture and will be terminated with 50
W to ground
instead of a standard HSTL configuration (Figure 7). To ensure the
tight skew specification is realized, both sides of the differential output
need to be terminated identically into 50
W even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
Designers can take advantage of the EP809’s performance to
distribute low skew clocks across the backplane of the board. Both
clock inputs may be singleend driven by biasing the nondriven pin
in an input pair (Figure 8).
Features
100 ps Typical DevicetoDevice Skew
15 ps Typical within Device Skew
HSTL Compatible Outputs Drive 50 W to GND with no
Offset Voltage
Maximum Frequency > 750 MHz
850 ps Typical Propagation Delay
Fully Compatible with Micrel SY89809L
PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V
with GND = 0 V, VCCO = 1.6 V to 2.0 V
Open Input Default State
PbFree Packages are Available
32
1
MC100
AWLYYWWG
EP809
32LEAD LQFP
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
32
1
MC100
EP809
AWLYYWWG
G
1
QFN32
MN SUFFIX
CASE 488AM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP809FAR2 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V HSTL/PECL- HSTL RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100EP809FAR2G | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V HSTL/PECL- HSTL Clk Driver w/LVTTL RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100EP809MNG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 BBG ECL HSTL PECL IN HSTL RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100EP809MNR4G | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 BBG ECL HSTL PECL IN HSTL RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100EP89D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Evaluation Board Manual for High Frequency SOIC 8 |
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