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參數資料
| 型號： | MC100ES6039DWR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 1.27 MM PITCH, MS-013AC, SOIC-20 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 377K |
| 代理商： | MC100ES6039DWR2 |
MC100ES6039
Rev 2, 06/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V ECL/PECL/HSTL/LVDS
÷2/4,
÷4/6 Clock Generation Chip
The MC100ES6039 is a low skew
÷2/4, ÷4/6 clock generation chip designed
explicitly for low skew clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output edges are all precisely
aligned. The device can be driven by either a differential or single-ended ECL or,
if positive power supplies are used, LVPECL input signals. In addition, by using
the VBB output, a sinusoidal source can be AC coupled into the device.
The common enable (EN) is synchronous so that the internal dividers will only
be enabled/disabled when the internal clock is already in the LOW state. This
avoids any chance of generating a runt clock pulse on the internal clock when the
device is enabled/disabled as can happen with an asynchronous control. The
internal enable flip-flop is clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the negative edge of the clock
input.
Upon startup, the internal flip-flops will attain a random state; therefore, for
systems which utilize multiple ES6039s, the master reset (MR) input must be
asserted to ensure synchronization. For systems which only use one ES6039,
the MR pin need not be exercised as the internal divider design ensures
synchronization between the
÷2/4 and the ÷4/6 outputs of a single device. All VCC
and VEE pins must be externally connected to power supply to guarantee proper
operation.
The 100ES Series contains temperature compensation.
Features
Maximum Frequency >1.0 GHz Typical
50 ps Output-to-Output Skew
PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V
ECL Mode Operating Range: VCC = 0 V with VEE = –3.135 V to –3.8 V
Open Input Default State
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
VBB Output
LVDS and HSTL Input Compatible
20-Lead Pb-Free Package Available
MC100ES6039
ORDERING INFORMATION
Device
Package
MC100ES6039DW
SO-20
MC100ES6039DWR2
SO-20
MC100ES6039EG
SO-20 (Pb-Free)
MC100ES6039EGR2
SO-20 (Pb-Free)
DW SUFFIX
20-LEAD SOIC PACKAGE
CASE 751D-07
EG SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 751D-07
DATA SHEET
MC100ES6039
IDT 3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6 Clock Generation Chip
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6039
1
3.3 V ECL/PECL/HSTL/LVDS ÷2/4,
÷4/6 Clock Generation Chip
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC100ES6039EG | 功能描述:IC CLK GENERATION CHIP 20-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MC100ES6039EGR2 | 功能描述:時鐘發生器及支持產品 FSL 1-4 LVPECL div 2 /4, div 4/6 Clock Ge RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100ES6056DT | 功能描述:IC CLOCK BUFFER MUX 2:1 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:100ES 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數:1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| MC100ES6056DTR2 | 功能描述:IC CLOCK MUX 2:1 3GHZ 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:100ES 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:管件 |
| MC100ES6056EG | 功能描述:時鐘發生器及支持產品 FSL Dual Diff LVPECL/LVDS 2:1 Mux RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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