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參數資料
| 型號： | MC100ES6056EGR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER |
| 中文描述： | 100E SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
| 封裝： | 1.27 MM PITCH, LEAD FREE, MS-013AC, SOIC-20 |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 727K |
| 代理商： | MC100ES6056EGR2 |
2.5V, 3.3V ECL/LVPECL/LVDS DUAL
DIFFERENTIAL 2:1 MULTIPLEXER
MC100ES6056
IDT / ICS
2:1 MULTIPLEXER
1
MC100ES6056 REV. 5 JULY 16, 2007
The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path
makes the device ideal for multiplexing low skew clock or other skew sensitive signals.
Multiple V
BB
pins are provided.
The V
BB
pin, an internally generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is connected to V
BB
as a
switching reference voltage. V
BB
may also rebias AC coupled inputs. When used,
decouple V
BB
and V
CC
via a 0.01
μ
F capacitor and limit current sourcing or sinking to 0.5
mA. When not used, V
BB
should be left open.
The device features both individual and common select inputs to address both data
path and random logic applications.
The 100ES Series contains temperature compensation.
Features
360 ps Typical Propagation Delays
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
ECL Mode Operating Range: V
CC
= 0 V with V
EE
= –2.375 V to –3.8 V
Open Input Default State
Separate and Common Select
Q Output Will Default LOW with Inputs Open or at V
EE
V
BB
Outputs
LVDS Input Compatible
20-Lead Pb-Free Package Available
ORDERING INFORMATION
Device
Package
MC100ES6056DT
TSSOP-20
MC100ES6056DTR2
TSSOP-20
MC100ES6056EJ
TSSOP-20 (Pb-Free)
MC100ES6056EJR2
TSSOP-20 (Pb-Free)
MC100ES6056EG
MC100ES6056EGR2
SOIC-20 (Pb-Free)
SOIC-20 (Pb-Free)
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
EG SUFFIX
20-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751D-07
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
4
3
5
6
7
8
9
10
2
1
17
18
16
15
14
13
12
11
19
20
1
0
1
0
V
CC
Q0
Q0
SEL0COM_SEL SEL1
V
CC
Q1
Q1
V
EE
D0a
D0a
V
BB0
D0b
D0b
D1a
D1a
V
BB1
D1b
D1b
Figure 1. 20-Lead Pinout
(Top View)
and Logic Diagram
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC100ES6056EJ | 功能描述:時鐘驅動器及分配 FSL Dual Diff LVPECL/LVDS 2:1 Mux RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100ES6056EJR2 | 功能描述:時鐘發生器及支持產品 FSL Dual Diff LVPECL/LVDS 2:1 Mux RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100ES60T22D | 功能描述:IC DUAL TRANSLATOR 3.3V 8-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:100ES 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| MC100ES60T22EF | 功能描述:轉換 - 電壓電平 FSL LVTTL/LVCMOS :Diff LVPECL Trans. RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100ES60T22EFR2 | 功能描述:轉換 - 電壓電平 FSL LVTTL/LVCMOS :Diff LVPECL Trans. RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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