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參數資料
| 型號： | MC10131P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Parallel-Load 8-Bit Shift Registers 16-CFP -55 to 125 |
| 中文描述： | 10K SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 111K |
| 代理商： | MC10131P |
SEMICONDUCTOR TECHNICAL DATA
3–8
REV 5
Motorola, Inc. 1996
3/93
The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S)
and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop
may be clocked separately by holding the common clock in the low state and
using the enable inputs for the clocking function. If the common clock is to be
used to clock the flip–flop, the Clock Enable inputs must be in the low state. In
this case, the enable inputs perform the function of controlling the common
clock.
The output states of the flip–flop change on the positive transition of the
clock. A change in the information present at the data (D) input will not affect the
output information at any other time due to master slave construction.
PD= 235 mW typ/pkg (No Load)
FTog= 160 MHz typ
tpd= 3.0 ns typ
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
S1 5
D1 7
CE1 6
R1 4
CC 9
R2 13
CE2 11
D2 10
S2 12
Q1
Q1
Q2
Q2
2
3
14
15
CLOCKED TRUTH TABLE
C
L
H
H
R–S TRUTH TABLE
R
S
L
L
L
H
H
L
H
H
D
X
L
H
Qn+1
Qn
L
H
Qn+1
Qn
H
L
N.D.
C = CE + CC.A clock H is a clock transition from a
low to a high state.
N.D. = Not Defined
DIP
PIN ASSIGNMENT
VCC1
Q1
Q1
R1
S1
CE1
D1
VEE
VCC2
Q2
Q2
R2
S2
CE2
D2
CC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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