參數資料
| 型號： | MC14012BFELG |
| 廠商： | ON Semiconductor |
| 文件頁數： | 1/8頁 |
| 文件大小： | 0K |
| 描述： | IC GATE NAND DUAL P/N 14SOEIAJ |
| 標準包裝： | 2,000 |
| 系列： | 4000B |
| 邏輯類型： | 與非門 |
| 電路數： | 2 |
| 輸入數： | 4 |
| 電源電壓： | 3 V ~ 18 V |
| 電流 - 靜態（最大值）： | 1µA |
| 輸出電流高，低： | 8.8mA，8.8mA |
| 邏輯電平 - 低： | 1.5 V ~ 4 V |
| 邏輯電平 - 高： | 3.5 V ~ 11 V |
| 額定電壓和最大 CL 時的最大傳播延遲： | 100ns @ 15V，50pF |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 供應商設備封裝： | SOEIAJ-14 |
| 封裝/外殼： | 14-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. 10
1
Publication Order Number:
MC14012B/D
MC14012B
Dual 4-Input NAND Gates
The MC14012B dual 4input NAND gates are constructed with
PChannel and NChannel enhancement mode devices in a single
monolithic structure (Complementary MOS). Their primary use is
where low power dissipation and/or high noise immunity is desired.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
PinforPin Replacements for Corresponding CD4000 Series B
Suffix Devices
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
MARKING
DIAGRAMS
1
14
PDIP14
P SUFFIX
CASE 646
MC14012BCP
AWLYYWWG
SOIC14
D SUFFIX
CASE 751A
1
14
14012BG
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
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