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參數資料
| 型號： | MC14518BDWR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | RJZ Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 09V; Output Voltage (Vdc): 09V; Power: 2W; 2W Single and Dual Outputs in DIP 14; 3kVDC and 4kVDC Isolation; Optional Continuous Short Circuit Protected; Custom Solutions Available; UL94V-0 Package Material; Efficiency up to 85% |
| 中文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數： | 4/8頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MC14518BDWR2 |
MC14518B
http://onsemi.com
4
(7.)
Characteristic
Symbol
V
DD
Min
Typ
(8.)
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q/Enable to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 215 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
280
115
80
560
230
160
ns
Reset to Q
t
PHL
= (1.7 ns/pF) C
L
+ 265 ns
t
PHL
= (0.66 ns/pF) C
L
+ 117 ns
t
PHL
= (0.66 ns/pF) C
L
+ 95 ns
t
PHL
5.0
10
15
—
—
—
330
130
90
650
230
170
ns
Clock Pulse Width
t
w(H)
t
w(L)
5.0
10
15
200
100
70
100
50
35
—
—
—
ns
Clock Pulse Frequency
f
cl
5.0
10
15
—
—
—
2.5
6.0
8.0
1.5
3.0
4.0
MHz
Clock or Enable Rise and Fall Time
t
THL
, t
TLH
5.0
10
15
—
—
—
—
—
—
15
5
4
μ
s
Enable Pulse Width
t
WH(E)
5.0
10
15
440
200
140
220
100
70
—
—
—
ns
Reset Pulse Width
t
WH(R)
5.0
10
15
280
120
90
125
55
40
—
—
—
ns
Reset Removal Time
t
rem
5.0
10
15
– 5
15
20
– 45
– 15
– 5
—
—
—
ns
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR
VARIABLE
WIDTH
C
L
C
L
C
L
C
L
V
DD
V
SS
V
SS
500
μ
F
0.01
μ
F
CERAMIC
20 ns
50%
10%
90%
20 ns
I
D
Q3
Q2
Q1
Q0
C
E
R
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