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參數資料
| 型號： | MC145193F |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | 1.1 GHZ PLL FREQUENCY SYNTHESIZER |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO20 |
| 封裝： | PLASTIC, SO-20 |
| 文件頁數： | 21/24頁 |
| 文件大?。?/td> | 240K |
| 代理商： | MC145193F |
M
2
M
S
F
F
1
2
7
8
9
10
15
16
17
18
23
24
25
26
31
32
C Register Bits of Device #2
in Figure 22
C Register Bits of Device #1
in Figure 22
*At this point, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.
C7
C6
C0
X
X
X
X
X
X
C7
C6
C0
*
ENB
CLK
Din
1
2
7
8
9
15
16
17
23
24
25
31
32
A Register bits of Device #2
in Figure 22
A Register Bits of Device #1
in Figure 22
A23
A22
A16
A15
A8
A7
A0
A23
A16
38
39
40
47
48
A9
A8
A0
*
ENB
CLK
Din
* At this point, the new bytes are transferred to the A registers of both devices and stored. Additionally, for both devices, the
13 LSBs in each of the first buffers of the R registers are transferred to the respective R register’s second buffer. Thus, the
R, N, and A counter can be presented new divide ratios at the same time. The first buffer of each R register is not affected.
Neither C register is affected.
Figure 23. Accessing the C Registers of
Two Cascaded MC145193 or MC145202–1 Devices
Figure 24. Accessing the A Registers of
Two Cascaded MC145193 or MC145202–1 Devices
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| MC14521B | 24-Stage Frequency Divider |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC14519BCL | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:LOGIC MUX, QUAD, 2-INPUT, CMOS, 16 Pin, Ceramic, DIP |
| MC14519BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14519BF | 制造商:Panasonic Industrial Company 功能描述:IC |
| MC1451CCP | 制造商:PMD 功能描述: |
| MC14520B | 制造商:Motorola Inc 功能描述: 制造商:ON Semiconductor 功能描述: |
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