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參數(shù)資料
型號: MC14530BD
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Dual 5-Input Majority Logic Gate
中文描述: 4000/14000/40000 SERIES, DUAL 5-INPUT MAJORITY LOGIC GATE, PDSO16
封裝: PLASTIC, SOIC-16
文件頁數(shù): 1/7頁
文件大?。?/td> 217K
代理商: MC14530BD
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14530B
The MC14530B dual five–input majority logic gate is constructed with
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Combinational and sequential logic expressions are
easily implemented with the majority logic gate, often resulting in fewer
components than obtainable with the more basic gates. This device can also
provide numerous logic functions by using the W and some of the logic (A
thru E) inputs as control inputs.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Schottky TTL Load Over the Rated Temperature Range
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Iin, Iout
Input or Output Current (DC or Transient),
– 0.5 to + 18.0
V
±
10
V
mA
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
LOGIC TABLE
INPUTS A B C D E
W
Z
For all combinations of inputs where three or
more inputs are logical “0”.
0
1
1
0
For all combinations of inputs where three or
more inputs are logical “1”.
0
0
1
1
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
TRUTH TABLE
M5
0
0
1
1
W
0
1
0
1
Z
1
0
0
1
VDD = PIN 16
VSS = PIN 8
A
B
C
D
E
W
1
2
3
4
5
6
Z
7
M5
A
B
C
D
E
M5
13
12
11
10
9
14
W
Z
15
* Z = M5
Z = M5
Z = M5
W = (ABC+ABD+ABE+ACD+
W = (
ACE+ADE+BCD+BCE+
W = (
BDE+CDE)
W
* M5 is a logical “1” if any three or more
inputs are logical “1”.
Exclusive NOR Exclusive OR
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