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參數資料
| 型號： | MC26LS30DR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Differential Quad Single-Ended (EIA-423-A) Line Drivers |
| 中文描述： | QUAD LINE DRIVER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數： | 3/16頁 |
| 文件大小： | 108K |
| 代理商： | MC26LS30DR2 |
MC26LS30
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS
(EIA–422–A differential mode, Pin 4
V
EE
= Gnd, unless otherwise noted. Pin numbers refer to SO–16 package only.)
0.8 V, –40
°
C
T
A
85
°
C, 4.75 V
V
CC
5.25 V,
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage (see Figure 1)
Differential, R
L
=
∞
, V
CC
= 5.25 V
Differential, R
L
= 100
, V
CC
= 4.75 V
Change in Differential Voltage, R
L
= 100
(Note 4.)
Offset Voltage, R
L
= 100
Change in Offset Voltage*, R
L
= 100
Output Current (each output)
Power Off Leakage, V
CC
= 0, –10 V
High Impedance Mode, V
CC
= 5.25 V, –10 V
Short Circuit Current (Note 2.)
High Output Shorted to Pin 5 (T
A
= 25
°
C)
High Output Shorted to Pin 5 (–40
°
C
Low Output Shorted to +6.0 V (T
A
= 25
°
C)
Low Output Shorted to +6.0 V (–40
°
C
Inputs
Low Level Voltage
High Level Voltage
Current @ V
in
= 2.4 V
Current @ V
in
= 15 V
Current @ V
in
= 0.4 V
Current, 0
V
in
15 V, V
CC
= 0
Clamp Voltage (I
in
= –12 mA)
Power Supply Current (V
CC
= +5.25 V, Outputs Open)
(0
Enable
V
CC
)
V
OD1
V
OD2
V
OD2
V
OS
V
OS
–
2.0
–
–
–
4.2
2.6
10
2.5
10
6.0
–
400
3.0
400
Vdc
Vdc
mVdc
Vdc
mVdc
V
O
+10 V
V
O
+10 V
T
A
+85
°
C)
T
A
+85
°
C)
I
OLK
I
OZ
I
SC–
I
SC–
I
SC+
I
SC+
–100
–100
–150
–150
60
50
0
0
–95
–
75
–
+100
+100
–60
–50
150
150
μ
A
mA
V
IL
V
IH
I
IH
I
IHH
I
IL
I
IX
V
IK
I
CC
–
2.0
–
–
–200
–
–1.5
–
–
0
0
–8.0
0
–
0.8
–
40
100
–
–
–
Vdc
Vdc
μ
A
Vdc
–
16
30
mA
TIMING CHARACTERISTICS
(EIA–422–A differential mode, Pin 4
unless otherwise noted.)
0.8 V, T
A
= 25
°
C, V
CC
= 5.0 V, V
EE
= Gnd, (Notes 1. and 3.)
Characteristic
Symbol
Min
Typ
Max
Unit
Differential Output Rise Time (Figure 3)
t
r
t
f
–
70
200
ns
Differential Output Fall Time (Figure 3)
–
70
200
ns
Propagation Delay Time – Input to Differential Output
Input Low to High (Figure 3)
Input High to Low (Figure 3)
t
PDH
t
PDL
–
–
90
90
200
200
ns
Skew Timing (Figure 3)
t
PDH
to t
PDL
for Each Driver
Max to Min t
PDH
Within a Package
Max to Min t
PDL
Within a Package
Enable Timing (Figure 4)
Enable to Active High Differential Output
Enable to Active Low Differential Output
Enable to 3–State Output From Active High
Enable to 3–State Output From Active Low
t
SK1
t
SK2
t
SK3
–
–
–
9.0
2.0
2.0
–
–
–
ns
t
PZH
t
PZL
t
PHZ
t
PLZ
–
–
–
–
150
190
80
110
300
350
350
300
ns
1. All voltages measured with respect to Pin 5.
2. Only one output shorted at a time, for not more than 1 second.
3. Typical values established at +25
°
C, V
CC
= +5.0 V, V
EE
= –5.0 V.
4. V
in
switched from 0.8 to 2.0 V.
5. Imbalance is the difference between
V
O2
with V
in
0.8 V and
V
O2
with V
in
2.0 V.
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