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參數(shù)資料
| 型號： | MC26LS30DR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Differential Quad Single-Ended (EIA-423-A) Line Drivers |
| 中文描述： | QUAD LINE DRIVER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 108K |
| 代理商： | MC26LS30DR2 |
MC26LS30
http://onsemi.com
5
Table 1
Inputs
Outputs
Operation
V
CC
V
EE
Mode
A
B
C
D
A
B
C
D
Differential
(EIA–422–A)
(EIA 422 A)
+5.0
Gnd
0
0
0
0
0
0
1
1
1
1
1
0
1
X
1
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
1
X
0
0
0
0
1
0
1
Z
1
0
1
0
1
0
0
0
1
0
Z
0
1
0
0
0
1
0
0
1
0
0
1
0
Z
0
0
0
1
0
0
1
1
0
1
Z
0
0
0
0
1
Single–Ended
S g e
(EIA–423–A)
(EIA 423 A)
+5.0
5 0
–5.0
5 0
X
0
X
X
X
X
X
X
Z
Z
Z
Z
X = Don’t Care
Z = High Impedance (Off)
Figure 1. Differential Output Test
Figure 2. Single–Ended Output Test
V
EE
Mode = 0
V
OS
R
L
R
L
/2
R
L
/2
C
L
V
in
(0.8 or 2.0 V)
V
CC
V
O
V
CC
V
OD2
Mode = 1
V
in
(0.8 or 2.0 V)
Figure 3. Differential Mode Rise
/
Fall Time and Data Propagation Delay
NOTES:
1. S.G. set to: f
2. t
SK1
=
t
PDH
–t
PDL
for each driver.
3. t
SK2
computed by subtracting the shortest t
PDH
from the longest t
PDH
of the 2 drivers within a package.
4. t
SK3
computed by subtracting the shortest t
PDL
from the longest t
PDL
of the 2 drivers within a package.
1.0 MHz; duty cycle = 50%; t
r
, t
f
,
10 ns.
10%
t
PDH
1.5 V
V
in
0 V
10%
50%
90%
t
f
t
PDL
t
r
90%
50%
V
out
1.5 V
+3.0 V
V
CC
V
in
S.G.
V
OD
500 pF
100
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