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參數(shù)資料
| 型號(hào)： | MC44007 |
| 廠商： | Motorola, Inc. |
| 英文描述： | CHROMA 4 VIDEO PROCESSOR |
| 中文描述： | 色度4視頻處理器 |
| 文件頁(yè)數(shù)： | 34/40頁(yè) |
| 文件大小： | 491K |
| 代理商： | MC44007 |
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MC44002 MC44007
34
MOTOROLA ANALOG IC DEVICE DATA
SSE, SS1, SS2
– These 3 bits select the signal input from
which the timebase synchronization is taken. The composite
video input has a high quality sync separator which has been
designed to cope with noise and interference on the video;
the RGB and Y2 inputs have simple single sync separators
which may also be used for synchronization.
T1, T2
–
The bits are used to modify the response of the
variable Low Pass Filter placed at the composite video inputs
(for PAL/NTSC signals) in order to compensate for IF filtering
and the Q of external sound traps.
P1, P2, P3
–
These 3 bits are used to adjust the Luma
peaking value. The amount of peaking indicated is with
respect to the gain at the minimum peaking value (P1, P2,
P3 = 111).
D1, D2, D3
–
These 3 bits are used to adjust the Luma
delay. The indicated delay is that from the video inputs (Pins
2 and 40) to the Y1 output. The amount of delay depends on
the composite video standard used if S–VHS is selected.
NT0, NT1, NT2
– These 3 bits are used in conjunction with
SSA for the selection of the matrix coefficients mode.
HGAIN1, HGAIN2
– These 2 bits are used to set the gain
of the horizontal phase detector. The high gain position is
used to acquire lock and for operation with a VCR. Setting
HGAIN1 to 0 also enables a horizontal sync window. The low
gain position is used for off–the–air signals.
The remaining control bits are used singularly and are
listed as follows:
T3
– When high, this bit enables the variable Low Pass
Filter at the video inputs. For optimum performance, T3 must
be set to 0 in S–VHS and SECAM modes, and to 1 in PAL
and NTSC. The filter response is set with bits T1, T2.
S-VHS
–
Set to 1 for normal composite video input to
Pin 2 or 40. In this mode, the luma–chroma separator is
active. Set to 0 for S–VHS (Y/C) operation at those pins. In
this mode, luma is to be applied to the selected video input
(with bit V1/V2), and chroma is to be applied to the other
input. The luma–chroma separator is bypassed.
FSI
–
Selects either 50 Hz or 100 Hz field rate. When bit is
low, 50 Hz operation is selected. No usable with NTSC.
BAI
–
This bit selects the number of blanked lines for
either 525 or 625 line standards.
INTSEL
– The vertical sync separator operates by starting
a counter counting up at the beginning of each sync pulse, a
field pulse being recognized only if the counter counts up to a
sufficiently high value. The control bit INTSEL is used in
taking the decision as to when a vertical sync pulse has been
detected. When low, the pulse is detected after 36
μ
s; when
high after 68
μ
s. This may find application with anti-copy
techniques used with some VCRs, which rely on a modified
or corrupted field sync to allow a TV with a short time
constant to display a stable picture. However, a VCR having
a longer time constant will be unable to lock to the vertical.
CALKILL
– Enables or disables the horizontal calibration
loop. The loop is normally enabled only during startup for
some seconds and when there is no signal present. The loop
may be disabled so long as the horizontal timebase is locked
to an incoming signal.
XS
–
Is used to change between the two external crystal
positions (Pins 32 and 33).
SSD
–
Forces system select to PAL level. Can be used to
override SECAM mode in the delay line. When low, SECAM
mode is enabled (MC44002 only).
VDI
– Either 4:3 or 16:9 display mode can be chosen using
this bit. When low, the 16:9 mode is enabled.
D EN
–
Enables or disables the RGB Fast Commutation
switch for the RGB inputs. When low, RGB inputs are
enabled.
Y1 EN
– Switches Y1 through to the color difference stage.
Y2 EN
–
Switches Y2 through to the color difference stage.
Test
–
When bit is low, enables continuous sampling by
the RGB output control loops throughout the entire field
period. Used only for testing the IC.
YX EN
– Enables the luma matrix allowing saturation
control in the color difference stage.
Norm
–
Alters the division ratio for the reference
frequency used by the horizontal calibration loop. Always
used when changing between 14.3 MHz and 17.7 MHz
crystals.
BRI EN
–
Used to switch on or off the “bright” sampling
pulses used by the RGB output loops. This feature was
originally introduced to prevent any backscatter from these
three bright lines in the field interval from getting into the
picture. Must be enabled when adjusting intensity Contrast or
Red, Green and Blue.
2x Fh
–
Line drive output is either standard 15.625 kHz
(15.750 kHz) or at double this rate.
H EN
–
Control bit enables horizontal drive pulse. This is
normally done automatically after the values stored in the
MCU nonvolatile memory have been read into the
MC44002/7 memory.
V1/V2
– To select between Video Inputs 1 and 2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC44007P | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:CHROMA 4 VIDEO PROCESSOR |
| MC4401 | 制造商:SHENZHENFREESCALE 制造商全稱(chēng):ShenZhen FreesCale Electronics. Co., Ltd 功能描述:P-Channel 30-V (D-S) MOSFET Low thermal impedance |
| MC44011 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Chroma 4 Multistandard Video Processor |
| MC44011FB | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR |
| MC44011FN | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Chroma 4 Multistandard Video Processor |
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