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參數資料
| 型號： | MC44144P |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | SUBCARRIER PHASE-LOCKED LOOP |
| 中文描述： | PHASE LOCKED LOOP, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數： | 3/8頁 |
| 文件大小： | 117K |
| 代理商： | MC44144P |
MC44144
3
MOTOROLA ANALOG IC DEVICE DATA
Crystal
Drive
4X Ref
Voltage
Control
Input
4X Ref
Out
VCO
1.0k
1.0k
1.0n
1.0n
Subcarrier
Output
4X
Subcarrier
Output
4
2
1
5
6
7
470p
5.0 to 25p
14.32/
17.73MHz
0.1
μ
47k
0.1
μ
2.6V
Subcarrier
Reference
Output
Gate Pulse
Clamp Out
Phase Det Out
Subcarrier
Reference
Clamp In
Video In
Divide by 4
Video Clamp
Voltage
Reference
Phase
Detector
Composite
Video
75
+ 5.0
Burst
Gate
8
3
Figure 2. Representative Schematic Diagram
FUNCTIONAL DESCRIPTION
The MC44144 is designed to implement the color sync
function in a video system. When provided NTSC/PAL
composite video or composite chroma and burst gate inputs,
the IC will phase–lock a Voltage Controlled Crystal Oscillator
(VCXO) to the color burst. Both 4X and 1X subcarrier
frequency outputs are provided by the IC. The VCXO
operates off of a 4X subcarrier crystal and The VCXO
operates off a 4X subcarrier crystal and is capable of at least
±
600 Hz of pull–in. The tradeoff for such a wide pull–in range
is a resultant “soft” lock, or a 3
°
phase shift per 100 Hz
changein oscillator free–run or input reference frequency.
In addition to providing the gate pulse for the MC44144
phase detector, the Burst Gate input also initiates a clamp
pulse that sets up the level of the composite video at the input
to the Phase Detector. The start and duration of the Gate
Pulse should be timed so that the pulse envelopes the color
burst of the video signal, but not so wide as to gate sync or
video into the Phase Detector.
The Phase Detector is enabled when the voltage at the
Burst Gate input (Pin 7) is above the nominal 2.2 V threshold.
While this makes possible the ability to lock to a color burst,
it does not exclude the possibility of lock to a constant
reference. If a constant source is to be the reference, the
Phase Detector can be permanently enabled by holding the
voltage on the Phase Detector input pin higher than the
threshold voltage.
The phase detector gain must be specified in two ways, for
a constant reference and for a burst–locked application. The
gain in a constant reference application is specified by the
maximum current output with the maximum phase error. For
a maximum phase error of
π
/2 radians the maximum current
available is approximately 200
μ
A. So the phase detector
gain is defined as,
KPD = 200/(
π
/2)(
μ
A/rad sec)
For a burst–locked application, the Phase Detector is
active for only the duration of the color burst. Therefore the
phase detector gain must be specified as an average gain
over a line period. In this case the phase detector gain for
NTSC and for PAL applications is,
KPDNTSC = (8/(
π
/2))(
μ
A/rad sec) and,
KPDPAL = (7/(
π
/2))(
μ
A/rad sec)
A suitable filter for both types of applications is shown in
the test schematic Figure 2. This same filter also works for
both NTSC and PAL applications.
The 4X subcarrier Voltage Controlled Crystal Oscillator
(VCXO) uses a design that enables the use of series or
parallel resonant types of crystals. Still, layout and crystal
positioning are critical as the oscillator frequency is sensitive
to shunt capacitance. Care should be taken to keep the
crystal close to the IC and crystal switching should be
avoided. A suitable parallel type crystal would meet the
specifications in Table 1.
A plot showing the VCXO gain is shown in Figure 1. From
this plot the gain must be estimated from the operating point.
KOPAL is the gain for PAL applications and KONTSC is the
gain for NTSC applications.
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