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參數資料
| 型號： | MC44355DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 消費家電 |
| 英文描述： | MULTI.STANDARD AND PAL/NTSC MODULATOR ICs |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, SO-20 |
| 文件頁數： | 11/20頁 |
| 文件大小： | 438K |
| 代理商： | MC44355DW |
MC44353 MC44354 MC44355
11
MOTOROLA ANALOG IC DEVICE DATA
Test Modes
Various test modes can be enabled, by means of bits
TB0–2 and X0–1. These operate by assigning some internal
signals on the UHF phase comparator output current sources
as outlined in the following 2 tables.
Table 1. Test Mode 1
Test Bits TB0 to TB2 are located in C0, bits 0 to 2:
TB2
TB1
TB0
State
Function
0
0
0
0
See Table Test Mode 2
0
0
1
1
Normal Operation, But Test
Pattern Geneartor Disabled
0
1
0
2
Upper Source On, Lower
Source Off
0
1
1
3
Lower Source On, Upper
Source Off
1
0
0
4
Normal Operation with
Inverted Charge Polarity
1
0
1
5
High Impedance
1
1
0
6
Test Ref divider on Upper
Source (Fref), Lower Source Off
1
1
1
7
Test Progr. divider on Lower
Source (Fout/2), Upper Source Off
Table 2. Test Mode 2
Bits X0 and X1 are located in FL, bits 0 and 1:
X1
X0
State
Function
0
0
0a
Normal Operation with Non–Inverted
Charge Pump Polarity
0
1
0b
Normal Inverted Operation (same as
mode 4), but Transient Output Inhibit
Disabled.
1
0
0c
Normal Inverted Operation (same as
mode 4), but Transient Output Inhibit
Circuitry Forced (output disabled).
1
1
0d
Normal Inverted Operation (same as
mode 4), but Transient Output Inhibit
counter Sped up (64 times).
In normal operation, the phase comparator pulls high if the
UHF frequency is too high, and pulls low when the UHF
frequency is too low. This mode is used when the tuning
voltage is generated by the internal inverting operational
amplifier, so in this case mode 4 (100) must be used.
Switching in mode 0d will reset the transient delay counter,
which will time out at an accelerated rate of 64 times the
normal rate.
Sound Section Test Modes
The Sound PLL is tested in a similar fashion, and
responds to States 6 and 7 by placing the output of the sound
PLL programmable divider on the upper current source.
Table 3. Sound Subcarrier Frequency
SFD1
SFD0
Sound Subcarrier Freq (MHz)
0
0
4.5
0
1
5.5
1
0
6.0
1
1
6.5
NOTE:
1.Bits SFD1–0 are located in C0 bits 4 and 3.
Figure 15. CCIR Test Line 330
*1.0
0.86
0.72
0.58
0.44
**0.3
Step 0
1
2
3
4
5
NOTE:
Not to scale
*100 IRE
** 1 IRE
V
40
–16
Approximately Characteristic of Standard
Independent Filter in conformity with CCIR Rec. 567
0
–4
–8
–12
0
1
2
3
MHz
4
5
a
f
D
Figure 16. Noise Measurement/Weighting Filter
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