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參數資料
型號: MC54HC74
廠商: Motorola, Inc.
英文描述: Dual D Flip-Flop with Set and Reset
中文描述: 雙D觸發器的設置和復位
文件頁數: 3/7頁
文件大小: 229K
代理商: MC54HC74
MC54/74HC74A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
Symbol
Parameter
Test Conditions
V
25 C
85 C
6.0
±
0.1
Unit
μ
A
μ
A
Iin
ICC
Maximum Input Leakage Current
Maximum Quiescent Supply
Vin = VCC or GND
Vin = VCC or GND
6.0
2.0
±
1.0
125 C
±
1.0
80
20
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
(Figures 1 and 4)
4.5
30
20
6.0
17
24
26
tPLH,
Maximum Propagation Delay, Set or Reset to Q or Q
2.0
6.0
105
18
130
21
160
27
ns
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
75
15
22
110
22
ns
Speed CMOS Data Book (DL129/D).
95
19
CPD
Power Dissipation Capacitance (Per Flip–Flop)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
39
pF
TIMING REQUIREMENTS
Guaranteed Limit
– 55 to
VCC
(Figure 3)
4.5
6.0
16
14
24
20
Minimum Hold Time, Clock to Data
2.0
6.0
3.0
3.0
3.0
3.0
20
17
3.0
3.0
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
2.0
8.0
8.0
8.0
ns
(Figure 1)
4.5
12
18
(Figure 2)
4.5
6.0
12
10
15
18
15
Maximum Input Rise and Fall Times
2.0
6.0
1000
400
1000
400
15
13
1000
400
相關PDF資料
PDF描述
MC74HC74AD Dual D Flip-Flop with Set and Reset
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MC74HC74AN Dual D Flip-Flop with Set and Reset
MC54HCT00AJ Quad 2-Input NAND Gate with LSTTL-Compatible Inputs
MC74HCT74AN Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs
相關代理商/技術參數
參數描述
MC54HC74AJ 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Dual D Flip-Flop with Set and Reset
MC54HC75J 制造商:Motorola Inc 功能描述:
MC54HC86AJ 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 2-Input Exclusive OR Gate
MC54HC86J 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 2-Input Exclusive OR Gate
MC54HCT00A 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 2-Input NAND Gate with LSTTL-Compatible Inputs
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