
Communications Processor (CP)
4-58
MC68302 USER’S MANUAL
MOTOROLA
5. Reception of an address character when working in multidrop mode
Figure 4-20. UART Receive Buffer Descriptor
The first word of the Rx BD contains the control and status bits.
NOTE
In the nonautomatic multidrop mode (UM1–UM0 = 01), the ad-
dress character will be written into the next buffer for comparison
by the user software.
An example of the UART receive process is shown in Figure 4-21. This figure shows the re-
sulting state of the Rx BDs after receipt of 10 characters, an idle period, and five charac-
ters—one with a framing error. The example assumes that MRBLR = 8 in the SCC
parameter RAM.
E—Empty
0 = The data buffer associated with this BD has been filled with received data, or data
reception has been aborted due to an error condition. The M68000 core is free to
examine or write to any fields of the BD.
1 = The data buffer associated with the BD is empty. This bit is used to signify that the
BD and its associated buffer are available to the CP. After it sets this bit, the
M68000 core should not write to any fields of this BD when this bit is set. Note that
the empty bit will remain set while the CP is currently filling the buffer with received
data.
X—External Buffer
0 = The buffer associated with this BD is in internal dual-port RAM.
1 = The buffer associated with this BD is in external memory.
W—Wrap (Final BD in Table)
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
receive incoming data into the first BD in the table, allowing the user to use fewer
than eight BDs to conserve internal RAM.
NOTE
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant behavior may occur.
15
E
14
X
13
W
12
I
11
C
10
A
9
M
8
ID
7
—
6
—
5
4
3
2
—
1
0
OFFSET + 0
OFFSET + 2
OFFSET + 4
BR
FR
PR
OV
CD
DATA LENGTH
OFFSET +6
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)