
Communications Processor (CP)
4-140
MC68302 USER’S MANUAL
MOTOROLA
Bit 7—This bit is reserved and should be set to zero.
SMD3–SMD0—SMC Mode Support
X00X =GCI—The monitor channel is not used.
001X = GCI—The monitor channel data and the A and E control bits are internally
controlled according to the monitor channel protocol.
101X = GCI—The monitor channel data and the A and E control bits are received and
transmitted transparently by the IMP.
X100 = IDL—The M and A channels are in hunt-on-zero mode.
X101 = IDL—Only the M channel is in hunt-on-zero mode.
X110 = IDL—Only the A channel is in hunt-on-zero mode.
X111 = IDL—Regular operation; no channel is in hunt-on-zero mode.
LOOP—Local Loopback Mode
0 = Normal mode
1 = Local loopback mode. In GCI mode, EN1 and EN2 must also be set.
EN2—SMC2 Enable
0 = Disable SMC2
1 = Enable SMC2
EN1—SMC1 Enable
0 = Disable SMC1
1 = Enable SMC1
4.7.3 SMC Commands
The following commands issued to the CP command register (see 4.3 Command Set) are
used only when GCI is selected for the serial channels physical interface.
TRANSMIT ABORT REQUEST Command
This receiver command may be issued when the IMP implements the monitor channel
protocol. When issued, the IMP sends an abort request on the A bit.
TIMEOUT Command
This transmitter command may be issued when the IMP implements the monitor channel
protocol. It is issued because the device is not responding or because GCI A bit errors are
detected. When issued, the IMP sends an abort request on the E bit.
4.7.4 SMC Memory Structure and Buffers Descriptors
The CP uses several memory structures and memory-mapped registers to communicate
with the M68000 core. All the structures detailed in the following paragraphs reside in the
dual-port RAM of the IMP (see Figure 3-4). The SMC buffer descriptors allow the user to
define one data byte at a time for each transmit channel and receive one data byte at a time
for each receive channel.