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參數資料
型號: MC68HC05C9A
廠商: Motorola, Inc.
元件分類: 8位微控制器
英文描述: 8-Bit Microcontroller(8位微控制器)
中文描述: 8位微控制器(8位微控制器)
文件頁數: 131/160頁
文件大小: 783K
代理商: MC68HC05C9A
Electrical Specifications
Serial Peripheral Interface Timing
MC68HC05C9A
Rev. 4.0
General Release Specification
MOTOROLA
Electrical Specifications
131
L
G
R
12.8 Serial Peripheral Interface Timing
Table 12-5. Serial Peripheral Interface Timing (V
DD
= 5.0 Vdc)*
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
Cycle Time
Master
Slave
Enable Lead Time
Master
Slave
Enable Lag Time
Master
Slave
Clock (SCK) High Time
Master
Slave
Clock (SCK) Low Time
Master
Slave
Data Setup Time (Inputs)
Master
Slave
Data Hold Time (Inputs)
Master
Slave
Slave Access Time (Time to Data Active from
High-Impedance State)
Slave Disable Time (Hold Time to High-Impedance State)
Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
Rise Time (20% V
DD
to 70% V
DD
, C
L
= 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
Fall Time (70% V
to 20% V
, C
= 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
f
OP
(
M
)
f
OP
(
S
)
dc
dc
0.5
2.1
f
OP
MHz
1
t
CYC
(
M
)
t
CYC
(
S
)
2.0
480
t
CYC
ns
2
t
LEAD
(
M
)
t
LEAD
(
S
)
240
ns
3
t
LAG
(
M
)
t
LAG
(
S
)
720
ns
4
t
W
(
SCKH
)
M
t
W
(
SCKH
)
S
340
190
ns
5
t
W
(
SCKL
)
M
t
W
(
SCKL
)
S
340
190
ns
6
t
SU
(
M
)
t
SU
(
S
)
100
100
ns
7
t
H
(
M
)
t
H
(
S
)
100
100
ns
8
t
A
0
120
ns
9
t
DIS
240
ns
10
t
V
(
M
)
t
V
(
S
)
0.25
240
t
CYC
(
M
)
11
t
HO
(
M
)
t
HO
(
S
)
0.25
0
t
CYC
(
M
)
ns
12
t
RM
t
RS
100
2.0
ns
μ
s
13
t
FM
t
FS
100
2.0
ns
μ
s
NOTES:
* V
= 5.0 Vdc
±
10%; V
SS
= 0 Vdc, T
A
= –40 to +85
°
C, unless otherwise noted. Refer to Figure 12-7 and Figure 12-8 for
timing diagrams.
Signal production depends on software.
Assumes 200 pF load on all SPI pins
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