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參數(shù)資料
| 型號(hào)： | MC68HC05X4 |
| 廠商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件頁(yè)數(shù)： | 34/156頁(yè) |
| 文件大小： | 926K |
| 代理商： | MC68HC05X4 |
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CPU
MC68HC05X4
34
CPU
MOTOROLA
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
Indexed, 8-Bit
Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
Indexed,16-Bit
Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
8-cpu
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05X4CDW | HCMOS Microcontroller Unit |
| MC68HC05X4DW | HCMOS Microcontroller Unit |
| MC68HC705X4 | HCMOS Microcontroller Unit |
| MC68HC705X4CDW | HCMOS Microcontroller Unit |
| MC68HC705X4DW | HCMOS Microcontroller Unit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05X4CDW | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05X4DW | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC08AB16A | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC08AB16AD | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC08AZ0 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Advance Information |
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