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參數資料
型號: MC68HC05X4CDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Microcontroller Unit
中文描述: 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數: 106/156頁
文件大小: 926K
代理商: MC68HC05X4CDW
Core Timer
MC68HC05X4 Rev 1.0
106
Core Timer
MOTOROLA
If the COP circuit times out, an internal reset is generated and the normal
reset vector is fetched. COP timeout is prevented by writing a ‘0’ to bit 0
of address $1FF0. When the COP is cleared, only the final
divide-by-eight stage is cleared (see
Figure 1
).
The COP function is a mask option, enabled or disabled during device
manufacture.
Core timer registers
Core timer control
and status register
(CTCSR)
CTOF — Core timer overflow
1 = This read-only flag is set whenever a core timer overflow
occurs.
0 = No core timer overflow has occurred.
This bit is set when the core timer counter register rolls over from $FF
to $00; an interrupt request will be generated if CTOE is set. When
set, the bit may be cleared by writing a ‘0’ to it.
RTIF — Real time interrupt flag
1 = This read-only flag is set when the pre-selected RTI period has
elapsed. The RTI period is selected using the RT0 and RT1
bits as shown in
Table 1
.
0 = The pre-selected RTI period has not elapsed.
Address:
$0008
Bit 7
6
5
4
3
2
1
Bit 0
CTOF
RTIF
CTOE
RTIE
0
0
RT1
RT0
Reset:
u
u
0
0
0
0
1
1
Figure 2. Core Timer Control/Status Register (CTCSR)
4-ctimer
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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