
Serial Peripheral Interface Module (SPI)
Queuing transmission data
MC68HC08AZ32
MOTOROLA
Serial Peripheral Interface Module (SPI)
229
Queuing transmission data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the SPI data
register only when the SPTE bit is high.
Figure 11
shows the timing
associated with doing back-to-back transmissions with the SPI (SPSCK
has CPHA: CPOL = 1:0).
Figure 11. SPRF/SPTE CPU interrupt timing
BIT
3
MOSI
SCK (CPHA:CPOL = ’1’:0)
SPTE
WRITE TO SPDR
1
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
3
1
2
2
3
5
SPRF
READ SPSCR
MSB BIT
6
BIT
5
BIT
4
BIT
2
BIT
1
LSB MSB BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
LSB MSB BIT
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
5
8
10
8
10
4
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
6
CPU READS SPSCR WITH SPRF BIT SET.
4
6
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
9
11
12 CPU READS SPDR, CLEARING SPRF BIT.
BIT
5
BIT
4
BYTE 1
BYTE 2
BYTE 3
7
12
READ SPDR
7
CPU READS SPDR, CLEARING SPRF BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
21-spi