
Index
MC68HC08AZ32
512
Index
MOTOROLA
MC68HC08AZ0
. . . . . . . . . . . . . . . . . .416
MC68HC08AZ16
. . . . . . . . . . . . . . . . .439
MC68HC08AZ24
. . . . . . . . . . . . .445
,
451
break character
. . . . . . . . . . . . . . . . . . . . .176
break interrupt
. . . . . . . . . . . . . . . . . . . .83
,
87
causes
. . . . . . . . . . . . . . . . . . . . . . . . .130
during wait mode
. . . . . . . . . . . . . . . . . .88
effects on COP
. . . . . . . . . . . . . . .132
,
154
effects on CPU
. . . . . . . . . . . . . . . .60
,
131
effects on DMA
. . . . . . . . . . . . . . . . . .132
effects on PIT
. . . . . . . . . . . . . . . . . . . .296
effects on SPI
. . . . . . . . . . . . . . . . . . . .233
effects on TIM
. . . . . . . . . . . . . . .132
,
282
effects on TIMA
. . . . . . . . . . . . . . . . . .258
effects on TIMA-6
. . . . . . . . . . . . . . . . .472
flag protection during
. . . . . . . . . . . . . . .87
break module
break address registers (BRKH/L)
. . . . . . .
130
–
133
break status and control register (BRK-
SCR)
. . . . . . . . . . . . .130
,
133
,
135
break signal
. . . . . . . . . . . . . . . . . . . . . . . .142
BRKA bit (break active bit)
. . . . . . . .130
,
133
BRKE bit (break enable bit)
. . . . . . . . . . . .133
bus frequency
. . . . . . . . . . . . . . . . . . . . . . .54
bus timing
. . . . . . . . . . . . . . . . . . . . . . . . . .75
C
C bit
CCR
. . . . . . . . . . . . . . . . . . . . . . . . . . . .59
CCR
C bit (carry/borrow flag)
. . . . . . . . . . . . .59
H bit (half-carry flag)
. . . . . . . . . . . . . . .58
I bit (interrupt mask)
. . . . . . . . . . . . . . . .58
N bit (negative flag)
. . . . . . . . . . . . . . . .59
V bit (overflow flag)
. . . . . . . . . . . . . . . .58
Z bit (zero flag)
. . . . . . . . . . . . . . . . . . . .59
CGM
base clock output (CGMOUT)
. . . . . . .108
clock signals
. . . . . . . . . . . . . . . . . . . . . .75
CPU interrupt (CGMINT)
. . . . . . . . . . .108
crystal oscillator circuit
. . . . . . . . . . . . . .99
external connections
. . . . . . . . . . . . . .106
interrupts
. . . . . . . . . . . . . . . . . . . . . . .116
phase-locked loop (PLL) circuit
. . . . . . .99
PLL bandwidth control register (PBWC)
. .
101
,
112
PLL control register (PCTL)
. . . . . . . . .110
PLL programming register (PPG)
. . . .114
CGM acquisition/lock time information
. . .403
CGM component information
. . . . . . . . . .402
CGM operating conditions
. . . . . . . . . . . .402
CGMRCLK signal
. . . . . . . . . . . . . . . . . . . .99
CGMRDV signal
. . . . . . . . . . . . . . . . . . . .100
CGMVDV signal
. . . . . . . . . . . . . . . . . . . .100
CGMXCLK signal
. . . . . . . . . . . . . . .151
–
152
duty cycle
. . . . . . . . . . . . . . . . . . . . . . .108
CGMXFC pin
. . . . . . . . . . . . . . . . . . . . . . . .17
CGND/EV
ss
pin
. . . . . . . . . . . . . . . . . . . . .236
CHxF bits (TIM channel interrupt flag bits)
. . .
265
,
289
CHxF bits (TIMA channel interrupt flag bits)
. .
480
CHxIE bits (TIM channel interrupt enable bits)
265
,
289
,
480
CHxMAX bits (TIM maximum duty cycle bits)
268
,
291
CHxMAX bits (TIMA maximum duty cycle
bits)
. . . . . . . . . . . . . . . . . . . . . . . .483
CLI instruction
. . . . . . . . . . . . . . . . . . . . . . .58
clock generator module (CGM)
. . . . . .96
,
123
block diagram
. . . . . . . . . . . . . . . . . . . .98
clock start-up
from POR
. . . . . . . . . . . . . . . . . . . . . . . .75
clock start-up from LVI reset
. . . . . . . . . . . .75
COCO
Conversions Complete Bit
. . . . . . . . . .494
COCO/IDMAS
Conversions complete/interrupt DMA se-
lect
. . . . . . . . . . . . . . . . . . . . . .308
condition code register (CCR)
. . . . . . .57
,
163
control timing
. . . . . . . . . . . . . . . . . . . . . . .397
COP bit (computer operating properly reset
bit)
. . . . . . . . . . . . . . . . . . . . . . . . .151
COP control register (COPCTL)
. . . .152
–
153
COP counter
. . . . . . . . . . . . . . .149
,
151
–
154