
Clock Generator Module (CGM)
MC68HC08AZ32
100
Clock Generator Module (CGM)
MOTOROLA
8.
Verify the choice of N and L by comparing f
VCLK
to f
VRS
and
f
VCLKDES
. For proper operation, f
VCLK
must be within the
application’s tolerance of f
VCLKDES
, and f
VRS
must be as close
as possible to f
VCLK
.
NOTE:
Exceeding the recommended maximum bus frequency or VCO
frequency can cause the MCU to “crash”.
9.
Program the PLL registers accordingly:
a. In the upper 4 bits of the PLL programming register
(PPG), program the binary equivalent of N.
b. In the lower 4 bits of the PLL programming register
(PPG), program the binary equivalent of L.
Special
programming
exceptions
The programming method described in
Programming the PLL
on page
99, does not account for two
possible exceptions — a value of zero for
N or L is meaningless when used in the equations given. To account for
these exceptions:
A zero value for N is interpreted exactly the same as a value of
one.
A zero value for L disables the PLL and prevents its selection as
the source for the base clock. (See
Base clock selector circuit
on
page 100).
Base clock
selector circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
10-cgm